/*******************************************************************************
 * File name: 		hdr_scb.h
 * Description: 	header file wit registers bits. Registers appears here
 *                according to their addresses- first APB peripherals starting
 *                from 0xE000 0000 and then AHB devices starting from 0xF000 0000.
 * Project:       ht
 * Project: 		-
 * Target: 			LPC2478
 * Compiler: 		arm-none-eabi-gcc
 * Date: 			2010-06-02
 * Author: 			Kuba
 * Based on: 		http://freddiechopin.info
 *******************************************************************************/

#ifndef HDR_SCB_H_
#define HDR_SCB_H_

/*==============================================================================
 Defines
==============================================================================*/

/*==============================================================================
 APB peripherals
==============================================================================*/
/*------------------------------------------------------------------------------
 Watchdog
------------------------------------------------------------------------------*/

/*------------------------------------------------------------------------------
 Timer
------------------------------------------------------------------------------*/
/* Interrupt Register- T[0/1/2/3]IR */
# define T_IR_MR0_INTRPT_bit              0
# define T_IR_MR1_INTRPT_bit              1
# define T_IR_MR2_INTRPT_bit              2
# define T_IR_MR3_INTRPT_bit              3
# define T_IR_CR0_INTRPT_bit              4
# define T_IR_CR1_INTRPT_bit              5
# define T_IR_CR2_INTRPT_bit              6
# define T_IR_CR3_INTRPT_bit              7

# define T_IR_MR0_INTRPT                  (1 << T_IR_MR0_INTRPT_bit)
# define T_IR_MR1_INTRPT                  (1 << T_IR_MR1_INTRPT_bit)
# define T_IR_MR2_INTRPT                  (1 << T_IR_MR2_INTRPT_bit)
# define T_IR_MR3_INTRPT                  (1 << T_IR_MR3_INTRPT_bit)
# define T_IR_CR0_INTRPT                  (1 << T_IR_CR0_INTRPT_bit)
# define T_IR_CR1_INTRPT                  (1 << T_IR_CR1_INTRPT_bit)
# define T_IR_CR2_INTRPT                  (1 << T_IR_CR2_INTRPT_bit)
# define T_IR_CR3_INTRPT                  (1 << T_IR_CR3_INTRPT_bit)

/* Timer Control Register- T[0/1/2/3]CR */
# define T_TCR_CNT_ENABLE_bit             0
# define T_TCR_CNT_RESET_bit              0

# define T_TCR_CNT_ENABLE                 (1 << T_TCR_CNT_ENABLE_bit)
# define T_TCR_CNT_RESET                  (1 << T_TCR_CNT_RESET_bit)

/* Match Control Register- T[0/1/2/3]MCR */
# define T_MCR_MR0I_bit                   0
# define T_MCR_MR0R_bit                   1
# define T_MCR_MR0S_bit                   2
# define T_MCR_MR1I_bit                   3
# define T_MCR_MR1R_bit                   4
# define T_MCR_MR1S_bit                   5
# define T_MCR_MR2I_bit                   6
# define T_MCR_MR2R_bit                   7
# define T_MCR_MR2S_bit                   8
# define T_MCR_MR3I_bit                   9
# define T_MCR_MR3R_bit                   10
# define T_MCR_MR3S_bit                   11

# define T_MCR_MR0I                       (1 << T_MCR_MR0I_bit)
# define T_MCR_MR0R                       (1 << T_MCR_MR0R_bit)
# define T_MCR_MR0S                       (1 << T_MCR_MR0S_bit)
# define T_MCR_MR1I                       (1 << T_MCR_MR1I_bit)
# define T_MCR_MR1R                       (1 << T_MCR_MR1R_bit)
# define T_MCR_MR1S                       (1 << T_MCR_MR1S_bit)
# define T_MCR_MR2I                       (1 << T_MCR_MR2I_bit)
# define T_MCR_MR2R                       (1 << T_MCR_MR2R_bit)
# define T_MCR_MR2S                       (1 << T_MCR_MR2S_bit)
# define T_MCR_MR3I                       (1 << T_MCR_MR3I_bit)
# define T_MCR_MR3R                       (1 << T_MCR_MR3R_bit)
# define T_MCR_MR3S                       (1 << T_MCR_MR3S_bit)

/* Capture Control Register T[0/1/2/3]CCR */
# define T_CCR_CAP0RE_bit                 0
# define T_CCR_CAP0FE_bit                 1
# define T_CCR_CAP0I_bit                  2
# define T_CCR_CAP1RE_bit                 3
# define T_CCR_CAP1FE_bit                 4
# define T_CCR_CAP1I_bit                  5

# define T_CCR_CAP0RE                     (1 << T_CCR_CAP0RE_bit)
# define T_CCR_CAP0FE                     (1 << T_CCR_CAP0FE_bit)
# define T_CCR_CAP0I                      (1 << T_CCR_CAP0I_bit)
# define T_CCR_CAP1RE                     (1 << T_CCR_CAP1RE_bit)
# define T_CCR_CAP1FE                     (1 << T_CCR_CAP1FE_bit)
# define T_CCR_CAP1I                      (1 << T_CCR_CAP1I_bit)

/* External Match Register- T[0/1/2/3]EMR */
# define T_EMR_EM0_bit                    0
# define T_EMR_EM1_bit                    1
# define T_EMR_EM2_bit                    2
# define T_EMR_EM3_bit                    3
# define T_EMR_EMC0_bit                   4
# define T_EMR_EMC1_bit                   6
# define T_EMR_EMC2_bit                   8
# define T_EMR_EMC3_bit                   10

# define T_EMR_EMC_NOP_value              0
# define T_EMR_EMC_CLEAR_value            1
# define T_EMR_EMC_SET_value              2
# define T_EMR_EMC_TOGGLE_value           3

# define T_EMR_EM0                        (1 << T_EMR_EM0_bit)
# define T_EMR_EM1                        (1 << T_EMR_EM1_bit)
# define T_EMR_EM2                        (1 << T_EMR_EM2_bit)
# define T_EMR_EM3                        (1 << T_EMR_EM3_bit)
# define T_EMR_EMC0_NOP                   (T_EMR_EMC_NOP_value << T_EMR_EMC0_bit)
# define T_EMR_EMC0_CLEAR                 (T_EMR_EMC_CLEAR_value << T_EMR_EMC0_bit)
# define T_EMR_EMC0_SET                   (T_EMR_EMC_SET_value << T_EMR_EMC0_bit)
# define T_EMR_EMC0_TOGGLE                (T_EMR_EMC_TOGGLE_value << T_EMR_EMC0_bit)
# define T_EMR_EMC1_NOP                   (T_EMR_EMC_NOP_value << T_EMR_EMC1_bit)
# define T_EMR_EMC1_CLEAR                 (T_EMR_EMC_CLEAR_value << T_EMR_EMC1_bit)
# define T_EMR_EMC1_SET                   (T_EMR_EMC_SET_value << T_EMR_EMC1_bit)
# define T_EMR_EMC1_TOGGLE                (T_EMR_EMC_TOGGLE_value << T_EMR_EMC1_bit)
# define T_EMR_EMC2_NOP                   (T_EMR_EMC_NOP_value << T_EMR_EMC2_bit)
# define T_EMR_EMC2_CLEAR                 (T_EMR_EMC_CLEAR_value << T_EMR_EMC2_bit)
# define T_EMR_EMC2_SET                   (T_EMR_EMC_SET_value << T_EMR_EMC2_bit)
# define T_EMR_EMC2_TOGGLE                (T_EMR_EMC_TOGGLE_value << T_EMR_EMC2_bit)
# define T_EMR_EMC3_NOP                   (T_EMR_EMC_NOP_value << T_EMR_EMC3_bit)
# define T_EMR_EMC3_CLEAR                 (T_EMR_EMC_CLEAR_value << T_EMR_EMC3_bit)
# define T_EMR_EMC3_SET                   (T_EMR_EMC_SET_value << T_EMR_EMC3_bit)
# define T_EMR_EMC3_TOGGLE                (T_EMR_EMC_TOGGLE_value << T_EMR_EMC3_bit)

/* Count Control Register- T[0/1/2/3]CTCR */
# define T_CTCR_MODE_bit                  0
# define T_CTCR_CNT_INPUT_SEL_bit         2

# define T_CTCR_MODE_TIMER_value          0
# define T_CTCR_MODE_COUNTER_RE_value     1
# define T_CTCR_MODE_COUNTER_FE_value     2
# define T_CTCR_MODE_COUNTER_BE_value     3

# define T_CTCR_CNT_INPUT_SEL_CAPN0_value 0
# define T_CTCR_CNT_INPUT_SEL_CAPN1_value 1

# define T_CTCR_MODE_TIMER                (T_CTCR_MODE_TIMER_value << T_CTCR_MODE_bit)
# define T_CTCR_MODE_COUNTER_RE           (T_CTCR_MODE_COUNTER_RE_value << T_CTCR_MODE_bit)
# define T_CTCR_MODE_COUNTER_FE           (T_CTCR_MODE_COUNTER_FE_value << T_CTCR_MODE_bit)
# define T_CTCR_MODE_COUNTER_BE           (T_CTCR_MODE_COUNTER_RE_value << T_CTCR_MODE_bit)

# define T_CTCR_CNT_INPUT_SEL_CAPN0       (T_CTCR_CNT_INPUT_SEL_CAPN0_value << T_CTCR_CNT_INPUT_SEL_bit)
# define T_CTCR_CNT_INPUT_SEL_CAPN1       (T_CTCR_CNT_INPUT_SEL_CAPN1_value << T_CTCR_CNT_INPUT_SEL_bit)

/*------------------------------------------------------------------------------
 UART
------------------------------------------------------------------------------*/
/* Line Control Register */
# define U_LCR_WORD_LENGTH_SELECT_bit        0
# define U_LCR_STOP_BIT_SELECT_bit           2
# define U_LCR_PARITY_ENABLE_bit             3
# define U_LCR_PARITY_SELECT_bit             4
# define U_LCR_BREAK_CONTROL_bit             6
# define U_LCR_DLAB_bit                      7

# define U_LCR_WORD_LENGTH_SELECT_5BIT_value 0
# define U_LCR_WORD_LENGTH_SELECT_6BIT_value 1
# define U_LCR_WORD_LENGTH_SELECT_7BIT_value 2
# define U_LCR_WORD_LENGTH_SELECT_8BIT_value 3
# define U_LCR_WORD_LENGTH_SELECT_5BIT       (U_LCR_WORD_LENGTH_SELECT_5BIT_value << U_LCR_WORD_LENGTH_SELECT_bit)
# define U_LCR_WORD_LENGTH_SELECT_6BIT       (U_LCR_WORD_LENGTH_SELECT_6BIT_value << U_LCR_WORD_LENGTH_SELECT_bit)
# define U_LCR_WORD_LENGTH_SELECT_7BIT       (U_LCR_WORD_LENGTH_SELECT_7BIT_value << U_LCR_WORD_LENGTH_SELECT_bit)
# define U_LCR_WORD_LENGTH_SELECT_8BIT       (U_LCR_WORD_LENGTH_SELECT_8BIT_value << U_LCR_WORD_LENGTH_SELECT_bit)

# define U_LCR_STOP_BIT_SELECT_1BIT_value    0
# define U_LCR_STOP_BIT_SELECT_2BIT_value    1
# define U_LCR_STOP_BIT_SELECT_1BIT          (U_LCR_STOP_BIT_SELECT_1BIT_value << U_LCR_STOP_BIT_SELECT_bit)
# define U_LCR_STOP_BIT_SELECT_2BIT          (U_LCR_STOP_BIT_SELECT_2BIT_value << U_LCR_STOP_BIT_SELECT_bit)

# define U_LCR_PARITY_ENABLE                 (1 << U_LCR_PARITY_ENABLE_bit)

# define U_LCR_PARITY_SELECT_ODD_value       0
# define U_LCR_PARITY_SELECT_EVEN_value      1
# define U_LCR_PARITY_SELECT_F1_value        2
# define U_LCR_PARITY_SELECT_F0_value        3
# define U_LCR_PARITY_SELECT_ODD             (U_LCR_PARITY_SELECT_ODD_value << U_LCR_PARITY_SELECT_bit)
# define U_LCR_PARITY_SELECT_EVEN            (U_LCR_PARITY_SELECT_EVEN_value << U_LCR_PARITY_SELECT_bit)
# define U_LCR_PARITY_SELECT_F1              (U_LCR_PARITY_SELECT_F1_value << U_LCR_PARITY_SELECT_bit)
# define U_LCR_PARITY_SELECT_F0              (U_LCR_PARITY_SELECT_F0_value << U_LCR_PARITY_SELECT_bit)

# define U_LCR_BREAK_CONTROL                 (1 << U_LCR_BREAK_CONTROL_bit)
# define U_LCR_DLAB                          (1 << U_LCR_DLAB_bit)

/* Fifo Control Register */
# define U_FCR_FIFO_ENABLE_bit               0
# define U_FCR_FIFO_RST_RX_bit               1                       /* Rx fifo reset */
# define U_FCR_FIFO_RST_TX_bit               2                       /* Tx fifo reset */
# define U_FCR_RX_FIFO_TRIGGER_LEVEL_bit     6                       /* interrupt trigger level */

# define U_FCR_FIFO_ENABLE                   (1 << U_FCR_FIFO_ENABLE_bit)
# define U_FCR_FIFO_RST_RX                   (1 << U_FCR_FIFO_RST_RX_bit)
# define U_FCR_FIFO_RST_TX                   (1 << U_FCR_FIFO_RST_TX_bit)

# define U_FCR_RX_FIFO_TRIGGER_LEVEL_1CHAR_value   0                    /* Trigger level 0 - 1 character */
# define U_FCR_RX_FIFO_TRIGGER_LEVEL_4CHAR_value   1                    /* Trigger level 1 - 4 characters */
# define U_FCR_RX_FIFO_TRIGGER_LEVEL_8CHAR_value   2                    /* Trigger level 2 - 8 characters */
# define U_FCR_RX_FIFO_TRIGGER_LEVEL_14CHAR_value  3                    /* Trigger level 3 - 14 character */

# define U_FCR_RX_FIFO_TRIGGER_LEVEL_1CHAR         (U_FCR_RX_FIFO_TRIGGER_LEVEL_1CHAR_value << U_FCR_RX_FIFO_TRIGGER_LEVEL_bit)
# define U_FCR_RX_FIFO_TRIGGER_LEVEL_4CHAR         (U_FCR_RX_FIFO_TRIGGER_LEVEL_4CHAR_value << U_FCR_RX_FIFO_TRIGGER_LEVEL_bit)
# define U_FCR_RX_FIFO_TRIGGER_LEVEL_8CHAR         (U_FCR_RX_FIFO_TRIGGER_LEVEL_8CHAR_value << U_FCR_RX_FIFO_TRIGGER_LEVEL_bit)
# define U_FCR_RX_FIFO_TRIGGER_LEVEL_14CHAR        (U_FCR_RX_FIFO_TRIGGER_LEVEL_14CHAR_value << U_FCR_RX_FIFO_TRIGGER_LEVEL_bit)

/* Interrupt Enable Register */
# define U_IER_INTERRUPT_EN_RBR_bit             0                    /* Reciver Buffer Register data available interrupt */
# define U_IER_INTERRUPT_EN_THRE_bit            1                    /* Transmit Holding Register interrupt */
# define U_IER_INTERRUPT_EN_RX_STATUS_bit       2
# define U_IER_INTERRUPT_EN_ABAUD_END_bit       8                    /* Auto baud end interrupt */
# define U_IER_INTERRUPT_EN_ABAUD_TIMEOUT_bit   9                    /* Auto baud timeout */

# define U_IER_INTERRUPT_EN_RBR                 (1 << U_IER_INTERRUPT_EN_RBR_bit)
# define U_IER_INTERRUPT_EN_THRE                (1 << U_IER_INTERRUPT_EN_THRE_bit)
# define U_IER_INTERRUPT_EN_RX_STATUS           (1 << U_IER_INTERRUPT_EN_RX_STATUS_bit)
# define U_IER_INTERRUPT_EN_ABAUD_END           (1 << U_IER_INTERRUPT_EN_ABAUD_END_bit)
# define U_IER_INTERRUPT_EN_ABAUD_TIMEOUT       (1 << U_IER_INTERRUPT_EN_ABAUD_TIMEOUT_bit)

/* Interrupt Identyfication Register */
# define U_IIR_INTERRUPT_STATUS_bit          0
# define U_IIR_INTERRUPT_ID_bit              1                       /* Interrupt identification */
/*# define U_IIR_FIFO_EN_bit                 6*/                     /* Fifo enable */
# define U_IIR_ABAUD_END_bit                 8                       /* End of auto-baud interrupt */
# define U_IIR_ABAUD_TIMEOUT_bit             9                       /* End of auto-baud interrupt */

# define U_IIR_INTERRUPT_ID_RLS_value        3                       /* RLS - Receive Line Status */
# define U_IIR_INTERRUPT_ID_RDA_value        2                       /* RLS - Receive Data Available */
# define U_IIR_INTERRUPT_ID_CTI_value        6                       /* CTI - Character Timeout Indicator */
# define U_IIR_INTERRUPT_ID_THRE_value       1                       /* THRE - Transmitter Holding Register Empty */
# define U_IIR_INTERRUPT_ID_mask             0x0E

# define U_IIR_INTERRUPT_STATUS              (1 << U_IIR_INTERRUPT_STATUS_bit)
# define U_IIR_INTERRUPT_ID_RLS              (U_IIR_INTERRUPT_ID_RLS_value << U_IIR_INTERRUPT_ID_bit)
# define U_IIR_INTERRUPT_ID_RDA              (U_IIR_INTERRUPT_ID_RDA_value << U_IIR_INTERRUPT_ID_bit)
# define U_IIR_INTERRUPT_ID_CTI              (U_IIR_INTERRUPT_ID_CTI_value << U_IIR_INTERRUPT_ID_bit)
# define U_IIR_INTERRUPT_ID_THRE             (U_IIR_INTERRUPT_ID_THRE_value << U_IIR_INTERRUPT_ID_bit)
# define U_IIR_ABAUD_END                     (1 << U_IIR_ABAUD_END_bit)
# define U_IIR_ABAUD_TIMEOUT                 (1 << U_IIR_ABAUD_TIMEOUT_bit)

/* Line Status Register */
# define U_LSR_RECEIVER_DATA_READY_bit       0                       /* Line Status Register- Receiver Data Ready */
# define U_LSR_OVERRUN_ERROR_bit             1                       /* Line Status Register- Overrun Error */
# define U_LSR_PARITY_ERROR_bit              2                       /* Line Status Register- Parity Error */
# define U_LSR_FRAMING_ERROR_bit             3                       /* Line Status Register- Framing Error */
# define U_LSR_BREAK_INTERRUPT_bit           4                       /* Line Status Register- Break Interrupt */
# define U_LSR_THR_EMPTY_bit                 5                       /* Line Status Register- Transmitter Holding Register Empty */
# define U_LSR_TRANSMITTER_EMPTY_bit         6                       /* Line Status Register- Transmitter Empty */
# define U_LSR_RX_FIFO_ERROR_bit             7                       /* Line Status Register- error in RX */

# define U_LSR_RECEIVER_DATA_READY        (1 << U_LSR_RECEIVER_DATA_READY_bit)
# define U_LSR_OVERRUN_ERROR              (1 << U_LSR_OVERRUN_ERROR_bit)
# define U_LSR_PARITY_ERROR               (1 << U_LSR_PARITY_ERROR_bit)
# define U_LSR_FRAMING_ERROR              (1 << U_LSR_FRAMING_ERROR_bit)
# define U_LSR_BREAK_INTERRUPT            (1 << U_LSR_BREAK_INTERRUPT_bit)
# define U_LSR_THR_EMPTY                  (1 << U_LSR_THR_EMPTY_bit)
# define U_LSR_TRANSMITTER_EMPTY          (1 << U_LSR_TRANSMITTER_EMPTY_bit)
# define U_LSR_RX_FIFO_ERROR              (1 << U_LSR_RX_FIFO_ERROR_bit)

/*------------------------------------------------------------------------------
 PWM
------------------------------------------------------------------------------*/
/*------------------------------------------------------------------------------
 I2C
------------------------------------------------------------------------------*/
/*------------------------------------------------------------------------------
 SPI
------------------------------------------------------------------------------*/
/* S0SPCR - SPI control register */
# define S0SPCR_BIT_ENABLE_bit				2
# define S0SPCR_CPHA_bit						3
# define S0SPCR_CPOL_bit						4
# define S0SPCR_MSTR_bit						5
# define S0SPCR_LSBF_bit						6
# define S0SPCR_SPIE_bit						7
# define S0SPCR_BITS_bit						8

# define S0SPCR_BITS_8_value					0x8
# define S0SPCR_BITS_9_value					0x9
# define S0SPCR_BITS_10_value					0xA
# define S0SPCR_BITS_11_value					0xB
# define S0SPCR_BITS_12_value					0xC
# define S0SPCR_BITS_13_value					0xD
# define S0SPCR_BITS_14_value					0xE
# define S0SPCR_BITS_15_value					0xF
# define S0SPCR_BITS_16_value					0x0

# define S0SPCR_BIT_ENABLE						(1 << S0SPCR_BIT_ENABLE_bit)
# define S0SPCR_CPHA								(1 << S0SPCR_CPHA_bit)
# define S0SPCR_CPOL								(1 << S0SPCR_CPOL_bit)
# define S0SPCR_MSTR								(1 << S0SPCR_MSTR_bit)
# define S0SPCR_LSBF								(1 << S0SPCR_LSBF_bit)
# define S0SPCR_SPIE								(1 << S0SPCR_SPIE_bit)
# define S0SPCR_BITS_8							(S0SPCR_BITS_8_value << S0SPCR_BITS_bit)
# define S0SPCR_BITS_9							(S0SPCR_BITS_9_value << S0SPCR_BITS_bit)
# define S0SPCR_BITS_10							(S0SPCR_BITS_10_value << S0SPCR_BITS_bit)
# define S0SPCR_BITS_11							(S0SPCR_BITS_11_value << S0SPCR_BITS_bit)
# define S0SPCR_BITS_12							(S0SPCR_BITS_12_value << S0SPCR_BITS_bit)
# define S0SPCR_BITS_13							(S0SPCR_BITS_13_value << S0SPCR_BITS_bit)
# define S0SPCR_BITS_14							(S0SPCR_BITS_14_value << S0SPCR_BITS_bit)
# define S0SPCR_BITS_15							(S0SPCR_BITS_15_value << S0SPCR_BITS_bit)
# define S0SPCR_BITS_16							(S0SPCR_BITS_16_value << S0SPCR_BITS_bit)

/* S0SPSR - SPI status register */
# define S0SPSR_ABRT_bit						3
# define S0SPSR_MODF_bit						4
# define S0SPSR_ROVR_bit						5
# define S0SPSR_WCOL_bit						6
# define S0SPSR_SPIF_bit						7

# define S0SPSR_ABRT								(1 << S0SPSR_ABRT_bit)
# define S0SPSR_MODF								(1 << S0SPSR_MODF_bit)
# define S0SPSR_ROVR								(1 << S0SPSR_ROVR_bit)
# define S0SPSR_WCOL								(1 << S0SPSR_WCOL_bit)
# define S0SPSR_SPIF								(1 << S0SPSR_SPIF_bit)

/* S0SPINT - SPI interrupt register */
# define S0SPINT_SPI_INT_FLAG_bit			0
# define S0SPINT_SPI_INT_FLAG					(1 << S0SPINT_SPI_INT_FLAG_bit)

/*------------------------------------------------------------------------------
 RTC
------------------------------------------------------------------------------*/
# define RTC_PREINT_VAL		0x00000894	/* Integer portion PREINT=int(PCLK/32768)-1=2196 -> 0x894 */
# define RTC_PREFRAC_VAL	0x00002200	/* Fractional portion PREFRAC=PCLK-((PREINT+1)*32768)=8704 -> 0x2200 */
# define CCR_CLKEN			0x01			/* Clock Control Register- bit Clock Enable */
# define CCR_CTCRST			0x02			/* Clock Control Register- bit Clock Tick Counter Reset */
# define ILR_RTCCIF			0x01			/* Interrupt Location Register- bit RTCCIF clears interrupt */

# define RTC_AMR_AMRSEC_bit		0		/* when 1, second value is not compared for the alarm */
# define RTC_AMR_AMRMIN_bit		1		/* when 1, minute value is not compared for the alarm */
# define RTC_AMR_AMRHOUR_bit		2		/* when 1, hour value is not compared for the alarm */
# define RTC_AMR_AMRDOM_bit		3		/* when 1, day of month value is not compared for the alarm */
# define RTC_AMR_AMRDOW_bit		4		/* when 1, day of week value is not compared for the alarm */
# define RTC_AMR_AMRDOY_bit		5		/* when 1, day of year value is not compared for the alarm */
# define RTC_AMR_AMRMON_bit		6		/* when 1, month value is not compared for the alarm */
# define RTC_AMR_AMRYEAR_bit		7		/* when 1, year value is not compared for the alarm */
# define RTC_AMR_AMRSEC				(1 << RTC_AMR_AMRSEC_bit)
# define RTC_AMR_AMRMIN				(1 << RTC_AMR_AMRMIN_bit)
# define RTC_AMR_AMRHOUR			(1 << RTC_AMR_AMRHOUR_bit)
# define RTC_AMR_AMRDOM				(1 << RTC_AMR_AMRDOM_bit)
# define RTC_AMR_AMRDOW				(1 << RTC_AMR_AMRDOW_bit)
# define RTC_AMR_AMRDOY				(1 << RTC_AMR_AMRDOY_bit)
# define RTC_AMR_AMRMON				(1 << RTC_AMR_AMRMON_bit)
# define RTC_AMR_AMRYEAR			(1 << RTC_AMR_AMRYEAR_bit)

# define RTC_CIIR_IMSEC_bit		0		/* when 1, sec increment generates an interrupt */
# define RTC_CIIR_IMMIN_bit		1		/* when 1, min increment generates an interrupt */
# define RTC_CIIR_IMHOUR_bit		2		/* when 1, hour increment generates an interrupt */
# define RTC_CIIR_IMDOM_bit		3		/* when 1, day of month increment generates an interrupt */
# define RTC_CIIR_IMDOW_bit		4		/* when 1, day of week generates an interrupt */
# define RTC_CIIR_IMDOY_bit		5		/* when 1, day of year increment generates an interrupt */
# define RTC_CIIR_IMMON_bit		6		/* when 1, month increment generates an interrupt */
# define RTC_CIIR_IMYEAR_bit		7		/* when 1, year increment generates an interrupt */
# define RTC_CIIR_IMSEC				(1 << RTC_CIIR_IMSEC_bit)
# define RTC_CIIR_IMMIN				(1 << RTC_CIIR_IMMIN_bit)
# define RTC_CIIR_IMHOUR			(1 << RTC_CIIR_IMHOUR_bit)
# define RTC_CIIR_IMDOM				(1 << RTC_CIIR_IMDOM_bit)
# define RTC_CIIR_IMDOW				(1 << RTC_CIIR_IMDOW_bit)
# define RTC_CIIR_IMDOY				(1 << RTC_CIIR_IMDOY_bit)
# define RTC_CIIR_IMMON				(1 << RTC_CIIR_IMMON_bit)
# define RTC_CIIR_IMYEAR			(1 << RTC_CIIR_IMYEAR_bit)

/*------------------------------------------------------------------------------
 GPIO
------------------------------------------------------------------------------*/
/* no need to write here */

/*------------------------------------------------------------------------------
 Pin Connect Block (pin function select registers)
 PINSELX_Y_Z : 	X is a number of PINSEL register
						Y is port number
						Z is pin number
------------------------------------------------------------------------------*/
# define PINSEL0_0_0_bit					0
# define PINSEL0_GPIO0_0_value			0
# define PINSEL0_RD1_value					1
# define PINSEL0_TXD3_value				2
# define PINSEL0_SDA1_value				3
# define PINSEL0_GPIO0_0					(PINSEL0_GPIO0_0_value << PINSEL0_0_0_bit)
# define PINSEL0_RD1							(PINSEL0_RD1_value << PINSEL0_0_0_bit)
# define PINSEL0_TXD3						(PINSEL0_TXD3_value << PINSEL0_0_0_bit)
# define PINSEL0_SDA1						(PINSEL0_SDA1_value << PINSEL0_0_0_bit)

# define PINSEL0_0_1_bit					2
# define PINSEL0_GPIO0_1_value			0
# define PINSEL0_TD1_value					1
# define PINSEL0_RXD3_value				2
# define PINSEL0_SCL1_value				3
# define PINSEL0_GPIO0_1					(PINSEL0_GPIO0_1_value << PINSEL0_0_1_bit)
# define PINSEL0_TD1							(PINSEL0_TD1_value << PINSEL0_0_1_bit)
# define PINSEL0_RXD3						(PINSEL0_RXD3_value << PINSEL0_0_1_bit)
# define PINSEL0_SCL1						(PINSEL0_SCL1_value << PINSEL0_0_1_bit)

# define PINSEL0_0_2_bit					4
# define PINSEL0_GPIO0_2_value			0
# define PINSEL0_TXD0_value				1
# define PINSEL0_GPIO0_2					(PINSEL0_GPIO0_2_value << PINSEL0_0_2_bit)
# define PINSEL0_TXD0						(PINSEL0_TXD0_value << PINSEL0_0_2_bit)

# define PINSEL0_0_3_bit					6
# define PINSEL0_GPIO0_3_value			0
# define PINSEL0_RXD0_value				1
# define PINSEL0_GPIO0_3					(PINSEL0_GPIO0_3_value << PINSEL0_0_3_bit)
# define PINSEL0_RXD0						(PINSEL0_RXD0_value << PINSEL0_0_3_bit)

# define PINSEL0_0_4_bit					8
# define PINSEL0_GPIO0_4_value			0
# define PINSEL0_I2SRX_CLK_value			1
# define PINSEL0_RD2_value					2
# define PINSEL0_CAP2_0_value				3
# define PINSEL0_GPIO0_4					(PINSEL0_GPIO0_4_value << PINSEL0_0_4_bit)
# define PINSEL0_I2SRX_CLK					(PINSEL0_I2SRX_CLK_value << PINSEL0_0_4_bit)
# define PINSEL0_RD2							(PINSEL0_RD2_value << PINSEL0_0_4_bit)
# define PINSEL0_CAP2_0						(PINSEL0_CAP2_0_value << PINSEL0_0_4_bit)

# define PINSEL0_0_5_bit					10
# define PINSEL0_GPIO0_5_value			0
# define PINSEL0_I2SRX_WS_value			1
# define PINSEL0_TD2_value					2
# define PINSEL0_CAP2_1_value				3
# define PINSEL0_GPIO0_5					(PINSEL0_GPIO0_5_value << PINSEL0_0_5_bit)
# define PINSEL0_I2SRX_WS					(PINSEL0_I2SRX_WS_value << PINSEL0_0_5_bit)
# define PINSEL0_TD2							(PINSEL0_TD2_value << PINSEL0_0_5_bit)
# define PINSEL0_CAP2_1						(PINSEL0_CAP2_1_value << PINSEL0_0_5_bit)

# define PINSEL0_0_6_bit					12
# define PINSEL0_GPIO0_6_value			0
# define PINSEL0_I2SRX_SDA_value			1
# define PINSEL0_SSEL1_value				2
# define PINSEL0_MAT2_0_value				3
# define PINSEL0_GPIO0_6					(PINSEL0_GPIO0_6_value << PINSEL0_0_6_bit)
# define PINSEL0_I2SRX_SDA					(PINSEL0_I2SRX_SDA_value << PINSEL0_0_6_bit)
# define PINSEL0_SSEL1						(PINSEL0_SSEL1_value << PINSEL0_0_6_bit)
# define PINSEL0_MAT2_0						(PINSEL0_MAT2_0_value << PINSEL0_0_6_bit)

# define PINSEL0_0_7_bit					14
# define PINSEL0_GPIO0_7_value			0
# define PINSEL0_I2STX_CLK_value			1
# define PINSEL0_SCK1_value				2
# define PINSEL0_MAT2_1_value				3
# define PINSEL0_GPIO0_7					(PINSEL0_GPIO0_7_value << PINSEL0_0_7_bit)
# define PINSEL0_I2STX_CLK					(PINSEL0_I2STX_CLK_value << PINSEL0_0_7_bit)
# define PINSEL0_SCK1						(PINSEL0_SCK1_value << PINSEL0_0_7_bit)
# define PINSEL0_MAT2_1						(PINSEL0_MAT2_1_value << PINSEL0_0_7_bit)

# define PINSEL0_0_8_bit					16
# define PINSEL0_GPIO0_8_value			0
# define PINSEL0_I2STX_WS_value			1
# define PINSEL0_MISO1_value				2
# define PINSEL0_MAT2_2_value				3
# define PINSEL0_GPIO0_8					(PINSEL0_GPIO0_8_value << PINSEL0_0_8_bit)
# define PINSEL0_I2STX_WS					(PINSEL0_I2STX_WS_value << PINSEL0_0_8_bit)
# define PINSEL0_MISO1						(PINSEL0_MISO1_value << PINSEL0_0_8_bit)
# define PINSEL0_MAT2_2						(PINSEL0_MAT2_2_value << PINSEL0_0_8_bit)

# define PINSEL0_0_9_bit					18
# define PINSEL0_GPIO0_9_value			0
# define PINSEL0_I2STX_SDA_value			1
# define PINSEL0_MOSI1_value				2
# define PINSEL0_MAT2_3_value				3
# define PINSEL0_GPIO0_9					(PINSEL0_GPIO0_9_value << PINSEL0_0_9_bit)
# define PINSEL0_I2STX_SDA					(PINSEL0_I2STX_SDA_value << PINSEL0_0_9_bit)
# define PINSEL0_MOSI1						(PINSEL0_MOSI1_value << PINSEL0_0_9_bit)
# define PINSEL0_MAT2_3						(PINSEL0_MAT2_3_value << PINSEL0_0_9_bit)

# define PINSEL0_0_10_bit					20
# define PINSEL0_GPIO0_10_value			0
# define PINSEL0_TXD2_value				1
# define PINSEL0_SDA2_value				2
# define PINSEL0_MAT3_0_value				3
# define PINSEL0_GPIO0_10					(PINSEL0_GPIO0_10_value << PINSEL0_0_10_bit)
# define PINSEL0_TXD2						(PINSEL0_TXD2_value << PINSEL0_0_10_bit)
# define PINSEL0_SDA2						(PINSEL0_SDA2_value << PINSEL0_0_10_bit)
# define PINSEL0_MAT3_0						(PINSEL0_MAT3_0_value << PINSEL0_0_10_bit)

# define PINSEL0_0_11_bit					22
# define PINSEL0_GPIO0_11_value			0
# define PINSEL0_RXD2_value				1
# define PINSEL0_SCL2_value				2
# define PINSEL0_MAT3_1_value				3
# define PINSEL0_GPIO0_11					(PINSEL0_GPIO0_11_value << PINSEL0_0_11_bit)
# define PINSEL0_RXD2						(PINSEL0_RXD2_value << PINSEL0_0_11_bit)
# define PINSEL0_SCL2						(PINSEL0_SCL2_value << PINSEL0_0_11_bit)
# define PINSEL0_MAT3_1						(PINSEL0_MAT3_1_value << PINSEL0_0_11_bit)

/* NOTE: PINSEL0 P0[12] defines second MISO1- uncomment if you need it */
# define PINSEL0_0_12_bit					24
# define PINSEL0_GPIO0_12_value			0
# define PINSEL0_USB_PPWR2_value			1
/* # define PINSEL0_MISO1_value			2 */
# define PINSEL0_AD0_6_value				3
# define PINSEL0_GPIO0_12					(PINSEL0_GPIO0_12_value << PINSEL0_0_12_bit)
# define PINSEL0_USB_PPWR2					(PINSEL0_USB_PPWR2_value << PINSEL0_0_12_bit)
/* # define PINSEL0_MISO1					(PINSEL0_MISO1_value << PINSEL0_0_12_bit) */
# define PINSEL0_AD0_6						(PINSEL0_AD0_6_value << PINSEL0_0_12_bit)

/* NOTE: PINSEL0 P0[13] defines second MOSI1- uncomment if you need it */
# define PINSEL0_0_13_bit					26
# define PINSEL0_GPIO0_13_value			0
# define PINSEL0_USB_UP_LED2_value		1
/* # define PINSEL0_MOSI1_value			2 */
# define PINSEL0_AD0_7_value				3
# define PINSEL0_GPIO0_13					(PINSEL0_GPIO0_13_value << PINSEL0_0_13_bit)
# define PINSEL0_USB_UP_LED2				(PINSEL0_USB_UP_LED2_value << PINSEL0_0_13_bit)
/* # define PINSEL0_MOSI1					(PINSEL0_MOSI1_value << PINSEL0_0_13_bit) */
# define PINSEL0_AD0_7						(PINSEL0_AD0_7_value << PINSEL0_0_13_bit)

/* NOTE: PINSEL0 P0[14] defines second SSEL1- uncomment if you need it */
# define PINSEL0_0_14_bit					28
# define PINSEL0_GPIO0_14_value			0
# define PINSEL0_USB_HSTEN2_value		1
# define PINSEL0_USB_CONN_value			2
/* # define PINSEL0_SSEL1_value			3 */
# define PINSEL0_GPIO0_14					(PINSEL0_GPIO0_14_value << PINSEL0_0_14_bit)
# define PINSEL0_USB_HSTEN2				(PINSEL0_USB_HSTEN2_value << PINSEL0_0_14_bit)
# define PINSEL0_USB_CONN					(PINSEL0_USB_CONN_value << PINSEL0_0_14_bit)
/* # define PINSEL0_SSEL1					(PINSEL0_SSEL1_value << PINSEL0_0_14_bit) */

# define PINSEL0_0_15_bit					30
# define PINSEL0_GPIO0_15_value			0
# define PINSEL0_TXD1_value				1
# define PINSEL0_SCK0_value				2
# define PINSEL0_SCK_value					3
# define PINSEL0_GPIO0_15					(PINSEL0_GPIO0_15_value << PINSEL0_0_15_bit)
# define PINSEL0_TXD1						(PINSEL0_TXD1_value << PINSEL0_0_15_bit)
# define PINSEL0_SCK0						(PINSEL0_SCK0_value << PINSEL0_0_15_bit)
# define PINSEL0_SCK							(PINSEL0_SCK_value << PINSEL0_0_15_bit)

/*------------------------------------------------------------------------------
 PINSEL1- Pin function select registers
------------------------------------------------------------------------------*/
# define PINSEL1_0_16_bit					0
# define PINSEL1_GPIO0_16_value			0
# define PINSEL1_RXD1_value				1
# define PINSEL1_SSEL0_value				2
# define PINSEL1_SSEL_value				3
# define PINSEL_GPIO0_16					(PINSEL1_GPIO0_16_value << PINSEL1_0_16_bit)
# define PINSEL1_RXD1						(PINSEL1_RXD1_value << PINSEL1_0_16_bit)
# define PINSEL1_SSEL0						(PINSEL1_SSEL0_value << PINSEL1_0_16_bit)
# define PINSEL1_SSEL						(PINSEL1_SSEL_value << PINSEL1_0_16_bit)

# define PINSEL1_0_17_bit					2
# define PINSEL1_GPIO0_17_value			0
# define PINSEL1_CTS1_value				1
# define PINSEL1_MISO0_value				2
# define PINSEL1_MISO_value				3
# define PINSEL1_GPIO0_17					(PINSEL1_GPIO0_17_value << PINSEL1_0_17_bit)
# define PINSEL1_CTS1						(PINSEL1_CTS1_value << PINSEL1_0_17_bit)
# define PINSEL1_MISO0						(PINSEL1_MISO0_value << PINSEL1_0_17_bit)
# define PINSEL1_MISO						(PINSEL1_MISO_value << PINSEL1_0_17_bit)

# define PINSEL1_0_18_bit					4
# define PINSEL1_GPIO0_18_value			0
# define PINSEL1_DCD1_value				1
# define PINSEL1_MOSI0_value				2
# define PINSEL1_MOSI_value				3
# define PINSEL1_GPIO0_18					(PINSEL1_GPIO0_18_value << PINSEL1_0_18_bit)
# define PINSEL1_DCD1						(PINSEL1_DCD1_value << PINSEL1_0_18_bit)
# define PINSEL1_MOSI0						(PINSEL1_MOSI0_value << PINSEL1_0_18_bit)
# define PINSEL1_MOSI						(PINSEL1_MOSI_value << PINSEL1_0_18_bit)

# define PINSEL1_0_19_bit					6
# define PINSEL1_GPIO0_19_value			0
# define PINSEL1_DSR1_value				1
# define PINSEL1_MCICLK_value				2
# define PINSEL1_SDA1_value				3
# define PINSEL1_GPIO0_19					(PINSEL1_GPIO0_19_value << PINSEL1_0_19_bit)
# define PINSEL1_DSR1						(PINSEL1_DSR1_value << PINSEL1_0_19_bit)
# define PINSEL1_MCICLK						(PINSEL1_MCICLK_value << PINSEL1_0_19_bit)
# define PINSEL1_SDA1						(PINSEL1_SDA1_value << PINSEL1_0_19_bit)

# define PINSEL1_0_20_bit					8
# define PINSEL1_GPIO0_20_value			0
# define PINSEL1_DTR1_value				1
# define PINSEL1_MCICMD_value				2
# define PINSEL1_SCL1_value				3
# define PINSEL1_GPIO0_20					(PINSEL1_GPIO0_20_value << PINSEL1_0_20_bit)
# define PINSEL1_DTR1						(PINSEL1_DTR1_value << PINSEL1_0_20_bit)
# define PINSEL1_MCICMD						(PINSEL1_MCICMD_value << PINSEL1_0_20_bit)
# define PINSEL1_SCL1						(PINSEL1_SCL1_value << PINSEL1_0_20_bit)

# define PINSEL1_0_21_bit					10
# define PINSEL1_GPIO0_21_value			0
# define PINSEL1_RI1_value					1
# define PINSEL1_MCIPWR_value				2
# define PINSEL1_RD1_value					3
# define PINSEL1_GPIO0_21					(PINSEL1_GPIO0_21_value << PINSEL1_0_21_bit)
# define PINSEL1_RI1							(PINSEL1_RI1_value << PINSEL1_0_21_bit)
# define PINSEL1_MCIPWR						(PINSEL1_MCIPWR_value << PINSEL1_0_21_bit)
# define PINSEL1_RD1							(PINSEL1_RD1_value << PINSEL1_0_21_bit)

# define PINSEL1_0_22_bit					12
# define PINSEL1_GPIO0_22_value			0
# define PINSEL1_RTS1_value				1
# define PINSEL1_MCIDAT0_value			2
# define PINSEL1_TD1_value					3
# define PINSEL1_GPIO0_22					(PINSEL1_GPIO0_22_value << PINSEL1_0_22_bit)
# define PINSEL1_RTS1						(PINSEL1_RTS1_value << PINSEL1_0_22_bit)
# define PINSEL1_MCIDAT0					(PINSEL1_MCIDAT0_value << PINSEL1_0_22_bit)
# define PINSEL1_TD1							(PINSEL1_TD1_value << PINSEL1_0_22_bit)

# define PINSEL1_0_23_bit					14
# define PINSEL1_GPIO0_23_value			0
# define PINSEL1_AD0_0_value				1
# define PINSEL1_I2SRX_CLK_value			2
# define PINSEL1_CAP3_0_value				3
# define PINSEL1_GPIO0_23					(PINSEL1_GPIO0_23_value << PINSEL1_0_23_bit)
# define PINSEL1_AD0_0						(PINSEL1_AD0_0_value << PINSEL1_0_23_bit)
# define PINSEL1_I2SRX_CLK					(PINSEL1_I2SRX_CLK_value << PINSEL1_0_23_bit)
# define PINSEL1_CAP3_0						(PINSEL1_CAP3_0_value << PINSEL1_0_23_bit)

# define PINSEL1_0_24_bit					16
# define PINSEL1_GPIO0_24_value			0
# define PINSEL1_AD0_1_value				1
# define PINSEL1_I2SRX_WS_value			2
# define PINSEL1_CAP3_1_value				3
# define PINSEL1_GPIO0_24					(PINSEL1_GPIO0_24_value << PINSEL1_0_24_bit)
# define PINSEL1_AD0_1						(PINSEL1_AD0_1_value << PINSEL1_0_24_bit)
# define PINSEL1_I2SRX_WS					(PINSEL1_I2SRX_WS_value << PINSEL1_0_24_bit)
# define PINSEL1_CAP3_1						(PINSEL1_CAP3_1_value << PINSEL1_0_24_bit)

# define PINSEL1_0_25_bit					18
# define PINSEL1_GPIO0_25_value			0
# define PINSEL1_AD0_2_value				1
# define PINSEL1_2SRX_SDA_value			2
# define PINSEL1_TXD3_value				3
# define PINSEL1_GPIO0_25					(PINSEL1_GPIO0_25_value << PINSEL1_0_25_bit)
# define PINSEL1_AD0_2						(PINSEL1_AD0_2_value << PINSEL1_0_25_bit)
# define PINSEL1_2SRX_SDA					(PINSEL1_2SRX_SDA_value << PINSEL1_0_25_bit)
# define PINSEL1_TXD3						(PINSEL1_TXD3_value << PINSEL1_0_25_bit)

# define PINSEL1_0_26_bit					20
# define PINSEL1_GPIO0_26_value			0
# define PINSEL1_AD0_3_value				1
# define PINSEL1_AOUT_value				2
# define PINSEL1_RXD3_value				3
# define PINSEL1_GPIO0_26					(PINSEL1_GPIO0_26_value << PINSEL1_0_26_bit)
# define PINSEL1_AD0_3						(PINSEL1_AD0_3_value << PINSEL1_0_26_bit)
# define PINSEL1_AOUT						(PINSEL1_AOUT_value << PINSEL1_0_26_bit)
# define PINSEL1_RXD3						(PINSEL1_RXD3_value << PINSEL1_0_26_bit)

# define PINSEL1_0_27_bit					22
# define PINSEL1_GPIO0_27_value			0
# define PINSEL1_SDA0_value				1
# define PINSEL1_GPIO0_27					(PINSEL1_GPIO0_27_value << PINSEL1_0_27_bit)
# define PINSEL1_SDA0						(PINSEL1_SDA0_value << PINSEL1_0_27_bit)

# define PINSEL1_0_28_bit					24
# define PINSEL1_GPIO0_28_value			0
# define PINSEL1_SCL0_value				1
# define PINSEL1_GPIO0_28					(PINSEL1_GPIO0_28_value << PINSEL1_0_28_bit)
# define PINSEL1_SCL0						(PINSEL1_SCL0_value << PINSEL1_0_28_bit)

# define PINSEL1_0_29_bit					26
# define PINSEL1_GPIO0_29_value			0
# define PINSEL1_USB_DPLUS1_value		1
# define PINSEL1_GPIO0_29					(PINSEL1_GPIO0_29_value << PINSEL1_0_29_bit)
# define PINSEL1_USB_DPLUS1				(PINSEL1_USB_DPLUS1_value << PINSEL1_0_29_bit)

# define PINSEL1_0_30_bit					28
# define PINSEL1_GPIO0_30_value			0
# define PINSEL1_USB_DMINUS1_value		1
# define PINSEL1_GPIO0_30					(PINSEL1_GPIO0_30_value << PINSEL1_0_30_bit)
# define PINSEL1_USB_DMINUS1				(PINSEL1_USB_DMINUS1_value << PINSEL1_0_30_bit)

# define PINSEL1_0_31_bit					30
# define PINSEL1_GPIO0_31_value			0
# define PINSEL1_USB_DPLUS2_value		1
# define PINSEL1_GPIO0_31					(PINSEL1_GPIO0_31_value << PINSEL1_0_31_bit)
# define PINSEL1_USB_DPLUS2				(PINSEL1_USB_DPLUS2_value << PINSEL1_0_31_bit)

/*------------------------------------------------------------------------------
 PINSEL2- Pin function select registers
------------------------------------------------------------------------------*/
# define PINSEL2_1_0_bit					0
# define PINSEL2_GPIO1_0_value			0
# define PINSEL2_ENET_TXD0_value			1
# define PINSEL2_GPIO1_0					(PINSEL2_GPIO1_0_value << PINSEL2_1_0_bit)
# define PINSEL2_ENET_TXD0					(PINSEL2_ENET_TXD0_value << PINSEL2_1_0_bit)

# define PINSEL2_1_1_bit					2
# define PINSEL2_GPIO1_1_value			0
# define PINSEL2_ENET_TXD1_value			1
# define PINSEL2_GPIO1_1					(PINSEL2_GPIO1_1_value << PINSEL2_1_1_bit)
# define PINSEL2_ENET_TXD1					(PINSEL2_ENET_TXD1_value << PINSEL2_1_1_bit)

# define PINSEL2_1_2_bit					4
# define PINSEL2_GPIO1_2_value			0
# define PINSEL2_ENET_TXD2_value			1
# define PINSEL2_MCICLK_value				2
# define PINSEL2_PWM0_1_value				3
# define PINSEL2_GPIO1_2					(PINSEL2_GPIO1_2_value << PINSEL2_1_2_bit)
# define PINSEL2_ENET_TXD2					(PINSEL2_ENET_TXD2_value << PINSEL2_1_2_bit)
# define PINSEL2_MCICLK						(PINSEL2_MCICLK_value << PINSEL2_1_2_bit)
# define PINSEL2_PWM0_1						(PINSEL2_PWM0_1_value << PINSEL2_1_2_bit)

# define PINSEL2_1_3_bit					6
# define PINSEL2_GPIO1_3_value			0
# define PINSEL2_ENET_TXD3_value			1
# define PINSEL2_MCICMD_value				2
# define PINSEL2_PWM0_2_value				3
# define PINSEL2_GPIO1_3					(PINSEL2_GPIO1_3_value << PINSEL2_1_3_bit)
# define PINSEL2_ENET_TXD3					(PINSEL2_ENET_TXD3_value << PINSEL2_1_3_bit)
# define PINSEL2_MCICMD						(PINSEL2_MCICMD_value << PINSEL2_1_3_bit)
# define PINSEL2_PWM0_2						(PINSEL2_PWM0_2_value << PINSEL2_1_3_bit)

# define PINSEL2_1_4_bit					8
# define PINSEL2_GPIO1_4_value			0
# define PINSEL2_ENET_TX_EN_value		1
# define PINSEL2_GPIO1_4					(PINSEL2_GPIO1_4_value << PINSEL2_1_4_bit)
# define PINSEL2_ENET_TX_EN				(PINSEL2_ENET_TX_EN_value << PINSEL2_1_4_bit)

# define PINSEL2_1_5_bit					10
# define PINSEL2_GPIO1_5_value			0
# define PINSEL2_ENET_TX_ER_value		1
# define PINSEL2_MCIPWR_value				2
# define PINSEL2_PWM0_3_value				3
# define PINSEL2_GPIO1_5					(PINSEL2_GPIO1_5_value << PINSEL2_1_5_bit)
# define PINSEL2_ENET_TX_ER				(PINSEL2_ENET_TX_ER_value << PINSEL2_1_5_bit)
# define PINSEL2_MCIPWR						(PINSEL2_MCIPWR_value << PINSEL2_1_5_bit)
# define PINSEL2_PWM0_3						(PINSEL2_PWM0_3_value << PINSEL2_1_5_bit)

# define PINSEL2_1_6_bit					12
# define PINSEL2_GPIO1_6_value			0
# define PINSEL2_ENET_TX_CLK_value		1
# define PINSEL2_MCIDAT0_value			2
# define PINSEL2_PWM0_4_value				3
# define PINSEL2_GPIO1_6					(PINSEL2_GPIO1_6_value << PINSEL2_1_6_bit)
# define PINSEL2_ENET_TX_CLK				(PINSEL2_ENET_TX_CLK_value << PINSEL2_1_6_bit)
# define PINSEL2_MCIDAT0					(PINSEL2_MCIDAT0_value << PINSEL2_1_6_bit)
# define PINSEL2_PWM0_4						(PINSEL2_PWM0_4_value << PINSEL2_1_6_bit)

# define PINSEL2_1_7_bit					14
# define PINSEL2_GPIO1_7_value			0
# define PINSEL2_ENET_COL_value			1
# define PINSEL2_MCIDAT1_value			2
# define PINSEL2_PWM0_5_value				3
# define PINSEL2_GPIO1_7					(PINSEL2_GPIO1_7_value << PINSEL2_1_7_bit)
# define PINSEL2_ENET_COL					(PINSEL2_ENET_COL_value << PINSEL2_1_7_bit)
# define PINSEL2_MCIDAT1					(PINSEL2_MCIDAT1_value << PINSEL2_1_7_bit)
# define PINSEL2_PWM0_5						(PINSEL2_PWM0_5_value << PINSEL2_1_7_bit)

# define PINSEL2_1_8_bit					16
# define PINSEL2_GPIO1_8_value			0
# define PINSEL2_ENET_CRS_DV_value		1
# define PINSEL2_GPIO1_8					(PINSEL2_GPIO1_8_value << PINSEL2_1_8_bit)
# define PINSEL2_ENET_CRS_DV				(PINSEL2_ENET_CRS_DV_value << PINSEL2_1_8_bit)

# define PINSEL2_1_9_bit					18
# define PINSEL2_GPIO1_9_value			0
# define PINSEL2_ENET_RXD0_value			1
# define PINSEL2_GPIO1_9					(PINSEL2_GPIO1_9_value << PINSEL2_1_9_bit)
# define PINSEL2_ENET_RXD0					(PINSEL2_ENET_RXD0_value << PINSEL2_1_9_bit)

# define PINSEL2_1_10_bit					20
# define PINSEL2_GPIO1_10_value			0
# define PINSEL2_ENET_RXD1_value			1
# define PINSEL2_GPIO1_10					(PINSEL2_GPIO1_10_value << PINSEL2_1_10_bit)
# define PINSEL2_ENET_RXD1					(PINSEL2_ENET_RXD1_value << PINSEL2_1_10_bit)

# define PINSEL2_1_11_bit					22
# define PINSEL2_GPIO1_11_value			0
# define PINSEL2_ENET_RXD2_value			1
# define PINSEL2_MCIDAT2_value			2
# define PINSEL2_PWM0_6_value				3
# define PINSEL2_GPIO1_11					(PINSEL2_GPIO1_11_value << PINSEL2_1_11_bit)
# define PINSEL2_ENET_RXD2					(PINSEL2_ENET_RXD2_value << PINSEL2_1_11_bit)
# define PINSEL2_MCIDAT2					(PINSEL2_MCIDAT2_value << PINSEL2_1_11_bit)
# define PINSEL2_PWM0_6						(PINSEL2_PWM0_6_value << PINSEL2_1_11_bit)

# define PINSEL2_1_12_bit					24
# define PINSEL2_GPIO1_12_value			0
# define PINSEL2_ENET_RXD3_value			1
# define PINSEL2_MCIDAT3_value			2
# define PINSEL2_PCAP0_0_value			3
# define PINSEL2_GPIO1_12					(PINSEL2_GPIO1_12_value << PINSEL2_1_12_bit)
# define PINSEL2_ENET_RXD3					(PINSEL2_ENET_RXD3_value << PINSEL2_1_12_bit)
# define PINSEL2_MCIDAT3					(PINSEL2_MCIDAT3_value << PINSEL2_1_12_bit)
# define PINSEL2_PCAP0_0					(PINSEL2_PCAP0_0_value << PINSEL2_1_12_bit)

# define PINSEL2_1_13_bit					26
# define PINSEL2_GPIO1_13_value			0
# define PINSEL2_ENET_RX_DV_value		1
# define PINSEL2_GPIO1_13					(PINSEL2_GPIO1_13_value	<< PINSEL2_1_13_bit)
# define PINSEL2_ENET_RX_DV				(PINSEL2_ENET_RX_DV_value << PINSEL2_1_13_bit)

# define PINSEL2_1_14_bit					28
# define PINSEL2_GPIO1_14_value			0
# define PINSEL2_ENET_RX_ER_value		1
# define PINSEL2_GPIO1_14					(PINSEL2_GPIO1_14_value << PINSEL2_1_14_bit)
# define PINSEL2_ENET_RX_ER				(PINSEL2_ENET_RX_ER_value << PINSEL2_1_14_bit)

# define PINSEL2_1_15_bit					30
# define PINSEL2_GPIO1_15_value			0
# define PINSEL2_ENET_REF_CLK_value		1
# define PINSEL2_GPIO1_15					(PINSEL2_GPIO1_15_value << PINSEL2_1_15_bit)
# define PINSEL2_ENET_REF_CLK				(PINSEL2_ENET_REF_CLK_value << PINSEL2_1_15_bit)

/*------------------------------------------------------------------------------
 PINSEL3- Pin function select registers
------------------------------------------------------------------------------*/
# define PINSEL3_1_16_bit					0
# define PINSEL3_GPIO1_16_value			0
# define PINSEL3_ENET_MDC_value			1
# define PINSEL3_GPIO1_16					(PINSEL3_GPIO1_16_value << PINSEL3_1_16_bit)
# define PINSEL3_ENET_MDC					(PINSEL3_ENET_MDC_value << PINSEL3_1_16_bit)

# define PINSEL3_1_17_bit					2
# define PINSEL3_GPIO1_17_value			0
# define PINSEL3_ENET_MDIO_value			1
# define PINSEL3_GPIO1_17					(PINSEL3_GPIO1_17_value << PINSEL3_1_17_bit)
# define PINSEL3_ENET_MDIO					(PINSEL3_ENET_MDIO_value << PINSEL3_1_17_bit)

# define PINSEL3_1_18_bit					4
# define PINSEL3_GPIO1_18_value			0
# define PINSEL3_USB_UP_LED1_value		1
# define PINSEL3_PWM1_1_value				2
# define PINSEL3_CAP1_0_value				3
# define PINSEL3_GPIO1_18					(PINSEL3_GPIO1_18_value	<< PINSEL3_1_18_bit)
# define PINSEL3_USB_UP_LED1				(PINSEL3_USB_UP_LED1_value << PINSEL3_1_18_bit)
# define PINSEL3_PWM1_1						(PINSEL3_PWM1_1_value << PINSEL3_1_18_bit)
# define PINSEL3_CAP1_0						(PINSEL3_CAP1_0_value << PINSEL3_1_18_bit)

# define PINSEL3_1_19_bit					6
# define PINSEL3_GPIO1_19_value			0
# define PINSEL3_USB_TX_E1_value			1
# define PINSEL3_USB_PPWR1_value			2
# define PINSEL3_CAP1_1_value				3
# define PINSEL3_GPIO1_19					(PINSEL3_GPIO1_19_value << PINSEL3_1_19_bit)
# define PINSEL3_USB_TX_E1					(PINSEL3_USB_TX_E1_value << PINSEL3_1_19_bit)
# define PINSEL3_USB_PPWR1					(PINSEL3_USB_PPWR1_value << PINSEL3_1_19_bit)
# define PINSEL3_CAP1_1						(PINSEL3_CAP1_1_value << PINSEL3_1_19_bit)

# define PINSEL3_1_20_bit					8
# define PINSEL3_GPIO1_20_value			0
# define PINSEL3_USB_TX_DP1_value		1
# define PINSEL3_PWM1_2_value				2
# define PINSEL3_SCK0_value				3
# define PINSEL3_GPIO1_20					(PINSEL3_GPIO1_20_value << PINSEL3_1_20_bit)
# define PINSEL3_USB_TX_DP1				(PINSEL3_USB_TX_DP1_value << PINSEL3_1_20_bit)
# define PINSEL3_PWM1_2						(PINSEL3_PWM1_2_value << PINSEL3_1_20_bit)
# define PINSEL3_SCK0						(PINSEL3_SCK0_value << PINSEL3_1_20_bit)

# define PINSEL3_1_21_bit					10
# define PINSEL3_GPIO1_21_value			0
# define PINSEL3_USB_TX_DM1_value		1
# define PINSEL3_PWM1_3_value				2
# define PINSEL3_SSEL0_value				3
# define PINSEL3_GPIO1_21					(PINSEL3_GPIO1_21_value << PINSEL3_1_21_bit)
# define PINSEL3_USB_TX_DM1				(PINSEL3_USB_TX_DM1_value << PINSEL3_1_21_bit)
# define PINSEL3_PWM1_3						(PINSEL3_PWM1_3_value << PINSEL3_1_21_bit)
# define PINSEL3_SSEL0						(PINSEL3_SSEL0_value << PINSEL3_1_21_bit)

# define PINSEL3_1_22_bit					12
# define PINSEL3_GPIO1_22_value			0
# define PINSEL3_USB_RCV1_value			1
# define PINSEL3_USB_PW1_value			2
# define PINSEL3_MAT1_0_value				3
# define PINSEL3_GPIO1_22					(PINSEL3_GPIO1_22_value << PINSEL3_1_22_bit)
# define PINSEL3_USB_RCV1					(PINSEL3_USB_RCV1_value << PINSEL3_1_22_bit)
# define PINSEL3_USB_PW1					(PINSEL3_USB_PW1_value << PINSEL3_1_22_bit)
# define PINSEL3_MAT1_0						(PINSEL3_MAT1_0_value << PINSEL3_1_22_bit)

# define PINSEL3_1_23_bit					14
# define PINSEL3_GPIO1_23_value			0
# define PINSEL3_USB_RX_DP1_value		1
# define PINSEL3_PWM1_4_value				2
# define PINSEL3_MISO0_value				3
# define PINSEL3_GPIO1_23					(PINSEL3_GPIO1_23_value << PINSEL3_1_23_bit)
# define PINSEL3_USB_RX_DP1				(PINSEL3_USB_RX_DP1_value << PINSEL3_1_23_bit)
# define PINSEL3_PWM1_4						(PINSEL3_PWM1_4_value << PINSEL3_1_23_bit)
# define PINSEL3_MISO0						(PINSEL3_MISO0_value << PINSEL3_1_23_bit)

# define PINSEL3_1_24_bit					16
# define PINSEL3_GPIO1_24_value			0
# define PINSEL3_USB_RX_DM1_value		1
# define PINSEL3_PWM1_5_value				2
# define PINSEL3_MOSI0_value				3
# define PINSEL3_GPIO1_24					(PINSEL3_GPIO1_24_value << PINSEL3_1_24_bit)
# define PINSEL3_USB_RX_DM1				(PINSEL3_USB_RX_DM1_value << PINSEL3_1_24_bit)
# define PINSEL3_PWM1_5						(PINSEL3_PWM1_5_value << PINSEL3_1_24_bit)
# define PINSEL3_MOSI0						(PINSEL3_MOSI0_value << PINSEL3_1_24_bit)

# define PINSEL3_1_25_bit					18
# define PINSEL3_GPIO1_25_value			0
# define PINSEL3_USB_LS1_value			1
# define PINSEL3_USB_HSTEN1_value		2
# define PINSEL3_MAT1_1_value				3
# define PINSEL3_GPIO1_25					(PINSEL3_GPIO1_25_value << PINSEL3_1_25_bit)
# define PINSEL3_USB_LS1					(PINSEL3_USB_LS1_value << PINSEL3_1_25_bit)
# define PINSEL3_USB_HSTEN1				(PINSEL3_USB_HSTEN1_value << PINSEL3_1_25_bit)
# define PINSEL3_MAT1_1						(PINSEL3_MAT1_1_value << PINSEL3_1_25_bit)

# define PINSEL3_1_26_bit					20
# define PINSEL3_GPIO1_26_value			0
# define PINSEL3_USB_SSPND1_value		1
# define PINSEL3_PWM1_6_value				2
# define PINSEL3_CAP0_0_value				3
# define PINSEL3_GPIO1_26					(PINSEL3_GPIO1_26_value << PINSEL3_1_26_bit)
# define PINSEL3_USB_SSPND1				(PINSEL3_USB_SSPND1_value << PINSEL3_1_26_bit)
# define PINSEL3_PWM1_6						(PINSEL3_PWM1_6_value << PINSEL3_1_26_bit)
# define PINSEL3_CAP0_0						(PINSEL3_CAP0_0_value << PINSEL3_1_26_bit)

# define PINSEL3_1_27_bit					22
# define PINSEL3_GPIO1_27_value			0
# define PINSEL3_USB_INT1_value			1
# define PINSEL3_USB_OVRCR1_value		2
# define PINSEL3_CAP0_1_value				3
# define PINSEL3_GPIO1_27					(PINSEL3_GPIO1_27_value << PINSEL3_1_27_bit)
# define PINSEL3_USB_INT1					(PINSEL3_USB_INT1_value << PINSEL3_1_27_bit)
# define PINSEL3_USB_OVRCR1				(PINSEL3_USB_OVRCR1_value << PINSEL3_1_27_bit)
# define PINSEL3_CAP0_1						(PINSEL3_CAP0_1_value << PINSEL3_1_27_bit)

# define PINSEL3_1_28_bit					24
# define PINSEL3_GPIO1_28_value			0
# define PINSEL3_USB_SCL1_value			1
# define PINSEL3_PCAP1_0_value			2
# define PINSEL3_MAT0_0_value				3
# define PINSEL3_GPIO1_28					(PINSEL3_GPIO1_28_value << PINSEL3_1_28_bit)
# define PINSEL3_USB_SCL1					(PINSEL3_USB_SCL1_value << PINSEL3_1_28_bit)
# define PINSEL3_PCAP1_0					(PINSEL3_PCAP1_0_value << PINSEL3_1_28_bit)
# define PINSEL3_MAT0_0						(PINSEL3_MAT0_0_value << PINSEL3_1_28_bit)

# define PINSEL3_1_29_bit					26
# define PINSEL3_GPIO1_29_value			0
# define PINSEL3_USB_SDA1_value			1
# define PINSEL3_PCAP1_1_value			2
# define PINSEL3_MAT0_1_value				3
# define PINSEL3_GPIO1_29					(PINSEL3_GPIO1_29_value << PINSEL3_1_29_bit)
# define PINSEL3_USB_SDA1					(PINSEL3_USB_SDA1_value << PINSEL3_1_29_bit)
# define PINSEL3_PCAP1_1					(PINSEL3_PCAP1_1_value << PINSEL3_1_29_bit)
# define PINSEL3_MAT0_1						(PINSEL3_MAT0_1_value << PINSEL3_1_29_bit)

# define PINSEL3_1_30_bit					28
# define PINSEL3_GPIO1_30_value			0
# define PINSEL3_USB_PWRD2_value			1
# define PINSEL3_VBUS_value				2
# define PINSEL3_AD0_4_value				3
# define PINSEL3_GPIO1_30					(PINSEL3_GPIO1_30_value << PINSEL3_1_30_bit)
# define PINSEL3_USB_PWRD2					(PINSEL3_USB_PWRD2_value << PINSEL3_1_30_bit)
# define PINSEL3_VBUS						(PINSEL3_VBUS_value << PINSEL3_1_30_bit)
# define PINSEL3_AD0_4						(PINSEL3_AD0_4_value << PINSEL3_1_30_bit)

# define PINSEL3_1_31_bit					30
# define PINSEL3_GPIO1_31_value			0
# define PINSEL3_USB_OVRCR2_value		1
# define PINSEL3_SCK1_value				2
# define PINSEL3_AD0_5_value				3
# define PINSEL3_GPIO1_31					(PINSEL3_GPIO1_31_value << PINSEL3_1_31_bit)
# define PINSEL3_USB_OVRCR2				(PINSEL3_USB_OVRCR2_value << PINSEL3_1_31_bit)
# define PINSEL3_SCK1						(PINSEL3_SCK1_value << PINSEL3_1_31_bit)
# define PINSEL3_AD0_5						(PINSEL3_AD0_5_value << PINSEL3_1_31_bit)

/*------------------------------------------------------------------------------
 PINSEL4- Pin function select registers
------------------------------------------------------------------------------*/
# define PINSEL4_2_0_bit					0
# define PINSEL4_GPIO2_0_value			0
# define PINSEL4_PWM1_1_value				1
# define PINSEL4_TXD1_value				2
# define PINSEL4_TRACECLK_value			3
# define PINSEL4_GPIO2_0					(PINSEL4_GPIO2_0_value 	<< PINSEL4_2_0_bit)
# define PINSEL4_PWM1_1						(PINSEL4_PWM1_1_value 	<< PINSEL4_2_0_bit)
# define PINSEL4_TXD1						(PINSEL4_TXD1_value 	<< PINSEL4_2_0_bit)
# define PINSEL4_TRACECLK					(PINSEL4_TRACECLK_value << PINSEL4_2_0_bit)

# define PINSEL4_2_1_bit					2
# define PINSEL4_GPIO2_1_value			0
# define PINSEL4_PWM1_2_value				1
# define PINSEL4_RXD1_value				2
# define PINSEL4_PIPESTAT0_value			3
# define PINSEL4_GPIO2_1					(PINSEL4_GPIO2_1_value 	<< PINSEL4_2_1_bit)
# define PINSEL4_PWM1_2						(PINSEL4_PWM1_2_value 	<< PINSEL4_2_1_bit)
# define PINSEL4_RXD1						(PINSEL4_RXD1_value 	<< PINSEL4_2_1_bit)
# define PINSEL4_PIPESTAT0					(PINSEL4_PIPESTAT0_value << PINSEL4_2_1_bit)

# define PINSEL4_2_2_bit					4
# define PINSEL4_GPIO2_2_value			0
# define PINSEL4_PWM1_3_value				1
# define PINSEL4_CTS1_value				2
# define PINSEL4_PIPESTAT1_value			3
# define PINSEL4_GPIO2_2					(PINSEL4_GPIO2_2_value 	<< PINSEL4_2_2_bit)
# define PINSEL4_PWM1_3						(PINSEL4_PWM1_3_value 	<< PINSEL4_2_2_bit)
# define PINSEL4_CTS1						(PINSEL4_CTS1_value  	<< PINSEL4_2_2_bit)
# define PINSEL4_PIPESTAT1					(PINSEL4_PIPESTAT1_value << PINSEL4_2_2_bit)

# define PINSEL4_2_3_bit					6
# define PINSEL4_GPIO2_3_value			0
# define PINSEL4_PWM1_4_value				1
# define PINSEL4_DCD1_value				2
# define PINSEL4_PIPESTAT2_value			3
# define PINSEL4_GPIO2_3					(PINSEL4_GPIO2_3_value 	<< PINSEL4_2_3_bit)
# define PINSEL4_PWM1_4						(PINSEL4_PWM1_4_value	<< PINSEL4_2_3_bit)
# define PINSEL4_DCD1						(PINSEL4_DCD1_value    	<< PINSEL4_2_3_bit)
# define PINSEL4_PIPESTAT2					(PINSEL4_PIPESTAT2_value << PINSEL4_2_3_bit)

# define PINSEL4_2_4_bit					8
# define PINSEL4_GPIO2_4_value			0
# define PINSEL4_PWM1_5_value				1
# define PINSEL4_DSR1_value				2
# define PINSEL4_TRACESYNC_value			3
# define PINSEL4_GPIO2_4					(PINSEL4_GPIO2_4_value << PINSEL4_2_4_bit)
# define PINSEL4_PWM1_5						(PINSEL4_PWM1_5_value << PINSEL4_2_4_bit)
# define PINSEL4_DSR1						(PINSEL4_DSR1_value << PINSEL4_2_4_bit)
# define PINSEL4_TRACESYNC					(PINSEL4_TRACESYNC_value << PINSEL4_2_4_bit)

# define PINSEL4_2_5_bit					10
# define PINSEL4_GPIO2_5_value			0
# define PINSEL4_PWM1_6_value				1
# define PINSEL4_DTR1_value				2
# define PINSEL4_TRACEPKT0_value			3
# define PINSEL4_GPIO2_5					(PINSEL4_GPIO2_5_value << PINSEL4_2_5_bit)
# define PINSEL4_PWM1_6						(PINSEL4_PWM1_6_value << PINSEL4_2_5_bit)
# define PINSEL4_DTR1						(PINSEL4_DTR1_value << PINSEL4_2_5_bit)
# define PINSEL4_TRACEPKT0					(PINSEL4_TRACEPKT0_value << PINSEL4_2_5_bit)

# define PINSEL4_2_6_bit					12
# define PINSEL4_GPIO2_6_value			0
# define PINSEL4_PCAP1_0_value			1
# define PINSEL4_RI1_value					2
# define PINSEL4_TRACEPKT1_value			3
# define PINSEL4_GPIO2_6					(PINSEL4_GPIO2_6_value << PINSEL4_2_6_bit)
# define PINSEL4_PCAP1_0					(PINSEL4_PCAP1_0_value << PINSEL4_2_6_bit)
# define PINSEL4_RI1							(PINSEL4_RI1_value << PINSEL4_2_6_bit)
# define PINSEL4_TRACEPKT1					(PINSEL4_TRACEPKT1_value << PINSEL4_2_6_bit)

# define PINSEL4_2_7_bit					14
# define PINSEL4_GPIO2_7_value			0
# define PINSEL4_RD2_value					1
# define PINSEL4_RTS1_value				2
# define PINSEL4_TRACEPKT2_value			3
# define PINSEL4_GPIO2_7					(PINSEL4_GPIO2_7_value << PINSEL4_2_7_bit)
# define PINSEL4_RD2							(PINSEL4_RD2_value << PINSEL4_2_7_bit)
# define PINSEL4_RTS1						(PINSEL4_RTS1_value << PINSEL4_2_7_bit)
# define PINSEL4_TRACEPKT2					(PINSEL4_TRACEPKT2_value << PINSEL4_2_7_bit)

# define PINSEL4_2_8_bit					16
# define PINSEL4_GPIO2_8_value			0
# define PINSEL4_TD2_value					1
# define PINSEL4_TXD2_value				2
# define PINSEL4_TRACEPKT3_value			3
# define PINSEL4_GPIO2_8					(PINSEL4_GPIO2_8_value << PINSEL4_2_8_bit)
# define PINSEL4_TD2							(PINSEL4_TD2_value << PINSEL4_2_8_bit)
# define PINSEL4_TXD2						(PINSEL4_TXD2_value << PINSEL4_2_8_bit)
# define PINSEL4_TRACEPKT3					(PINSEL4_TRACEPKT3_value << PINSEL4_2_8_bit)

# define PINSEL4_2_9_bit					18
# define PINSEL4_GPIO2_9_value			0
# define PINSEL4_USB_CONNECT1_value		1
# define PINSEL4_RXD2_value				2
# define PINSEL4_EXTIN0_value				3
# define PINSEL4_GPIO2_9					(PINSEL4_GPIO2_9_value << PINSEL4_2_9_bit)
# define PINSEL4_USB_CONNECT1				(PINSEL4_USB_CONNECT1_value << PINSEL4_2_9_bit)
# define PINSEL4_RXD2						(PINSEL4_RXD2_value << PINSEL4_2_9_bit)
# define PINSEL4_EXTIN0						(PINSEL4_EXTIN0_value << PINSEL4_2_9_bit)

# define PINSEL4_2_10_bit					20
# define PINSEL4_GPIO2_10_value			0
# define PINSEL4_USB_EINT0_value			1
# define PINSEL4_GPIO2_10					(PINSEL4_GPIO2_10_value << PINSEL4_2_10_bit)
# define PINSEL4_USB_EINT0					(PINSEL4_USB_EINT0_value << PINSEL4_2_10_bit)

# define PINSEL4_2_11_bit					22
# define PINSEL4_GPIO2_11_value			0
# define PINSEL4_EINT1_value				1
# define PINSEL4_MCIDAT1_value			2
# define PINSEL4_I2STX_CLK_value			3
# define PINSEL4_GPIO2_11					(PINSEL4_GPIO2_11_value << PINSEL4_2_11_bit)
# define PINSEL4_EINT1						(PINSEL4_EINT1_value << PINSEL4_2_11_bit)
# define PINSEL4_MCIDAT1					(PINSEL4_MCIDAT1_value << PINSEL4_2_11_bit)
# define PINSEL4_I2STX_CLK					(PINSEL4_I2STX_CLK_value << PINSEL4_2_11_bit)

# define PINSEL4_2_12_bit					24
# define PINSEL4_GPIO2_12_value			0
# define PINSEL4_EINT2_value				1
# define PINSEL4_MCIDAT2_value			2
# define PINSEL4_I2STX_WS_value			3
# define PINSEL4_GPIO2_12					(PINSEL4_GPIO2_12_value << PINSEL4_2_12_bit)
# define PINSEL4_EINT2						(PINSEL4_EINT2_value << PINSEL4_2_12_bit)
# define PINSEL4_MCIDAT2					(PINSEL4_MCIDAT2_value << PINSEL4_2_12_bit)
# define PINSEL4_I2STX_WS					(PINSEL4_I2STX_WS_value << PINSEL4_2_12_bit)

# define PINSEL4_2_13_bit					26
# define PINSEL4_GPIO2_13_value			0
# define PINSEL4_EINT3_value				1
# define PINSEL4_MCIDAT3_value			2
# define PINSEL4_I2STX_SDA_value			3
# define PINSEL4_GPIO2_13					(PINSEL4_GPIO2_13_value << PINSEL4_2_13_bit)
# define PINSEL4_EINT3						(PINSEL4_EINT3_value << PINSEL4_2_13_bit)
# define PINSEL4_MCIDAT3					(PINSEL4_MCIDAT3_value << PINSEL4_2_13_bit)
# define PINSEL4_I2STX_SDA					(PINSEL4_I2STX_SDA_value << PINSEL4_2_13_bit)

# define PINSEL4_2_14_bit					28
# define PINSEL4_GPIO2_14_value			0
# define PINSEL4_CS2_value					1
# define PINSEL4_CAP2_0_value				2
# define PINSEL4_SDA1_value				3
# define PINSEL4_GPIO2_14					(PINSEL4_GPIO2_14_value << PINSEL4_2_14_bit)
# define PINSEL4_CS2							(PINSEL4_CS2_value << PINSEL4_2_14_bit)
# define PINSEL4_CAP2_0						(PINSEL4_CAP2_0_value << PINSEL4_2_14_bit)
# define PINSEL4_SDA1						(PINSEL4_SDA1_value << PINSEL4_2_14_bit)

# define PINSEL4_2_15_bit					30
# define PINSEL4_GPIO2_15_value			0
# define PINSEL4_CS3_value					1
# define PINSEL4_CAP2_1_value				2
# define PINSEL4_SCL1_value				3
# define PINSEL4_GPIO2_15					(PINSEL4_GPIO2_15_value	<< PINSEL4_2_15_bit)
# define PINSEL4_CS3							(PINSEL4_CS3_value	<< PINSEL4_2_15_bit)
# define PINSEL4_CAP2_1						(PINSEL4_CAP2_1_value << PINSEL4_2_15_bit)
# define PINSEL4_SCL1						(PINSEL4_SCL1_value << PINSEL4_2_15_bit)
/*------------------------------------------------------------------------------
 PINSEL5- Pin function select registers
------------------------------------------------------------------------------*/
# define PINSEL5_2_16_bit					0
# define PINSEL5_GPIO2_16_value			0
# define PINSEL5_CAS_value					1
# define PINSEL5_GPIO2_16					(PINSEL5_GPIO2_16_value << PINSEL5_2_16_bit)
# define PINSEL5_CAS							(PINSEL5_CAS_value << PINSEL5_2_16_bit)

# define PINSEL5_2_17_bit					2
# define PINSEL5_GPIO2_17_value			0
# define PINSEL5_RAS_value					1
# define PINSEL5_GPIO2_17					(PINSEL5_GPIO2_17_value	<< PINSEL5_2_17_bit)
# define PINSEL5_RAS							(PINSEL5_RAS_value	<< PINSEL5_2_17_bit)

# define PINSEL5_2_18_bit					4
# define PINSEL5_GPIO2_18_value			0
# define PINSEL5_CLKOUT0_value			1
# define PINSEL5_GPIO2_18					(PINSEL5_GPIO2_18_value	<< PINSEL5_2_18_bit)
# define PINSEL5_CLKOUT0					(PINSEL5_CLKOUT0_value << PINSEL5_2_18_bit)

# define PINSEL5_2_19_bit					6
# define PINSEL5_GPIO2_19_value			0
# define PINSEL5_CLKOUT1_value			1
# define PINSEL5_GPIO2_19					(PINSEL5_GPIO2_19_value << PINSEL5_2_19_bit)
# define PINSEL5_CLKOUT1					(PINSEL5_CLKOUT1_value << PINSEL5_2_19_bit)

# define PINSEL5_2_20_bit					8
# define PINSEL5_GPIO2_20_value			0
# define PINSEL5_DYCS0_value				1
# define PINSEL5_GPIO2_20					(PINSEL5_GPIO2_20_value	<< PINSEL5_2_20_bit)
# define PINSEL5_DYCS0						(PINSEL5_DYCS0_value << PINSEL5_2_20_bit)

# define PINSEL5_2_21_bit					10
# define PINSEL5_GPIO2_21_value			0
# define PINSEL5_DYCS1_value				1
# define PINSEL5_GPIO2_21					(PINSEL5_GPIO2_21_value << PINSEL5_2_21_bit)
# define PINSEL5_DYCS1						(PINSEL5_DYCS1_value << PINSEL5_2_21_bit)

# define PINSEL5_2_22_bit					12
# define PINSEL5_GPIO2_22_value			0
# define PINSEL5_DYSC2_value				1
# define PINSEL5_CAP3_0_value				2
# define PINSEL5_SCK0_value				3
# define PINSEL5_GPIO2_22					(PINSEL5_GPIO2_22_value << PINSEL5_2_22_bit)
# define PINSEL5_DYSC2						(PINSEL5_DYSC2_value << PINSEL5_2_22_bit)
# define PINSEL5_CAP3_0						(PINSEL5_CAP3_0_value << PINSEL5_2_22_bit)
# define PINSEL5_SCK0						(PINSEL5_SCK0_value << PINSEL5_2_22_bit)

# define PINSEL5_2_23_bit					14
# define PINSEL5_GPIO2_23_value			0
# define PINSEL5_DYSC3_value				1
# define PINSEL5_CAP3_1_value				2
# define PINSEL5_SSEL0_value				3
# define PINSEL5_GPIO2_23					(PINSEL5_GPIO2_23_value	<< PINSEL5_2_23_bit)
# define PINSEL5_DYSC3						(PINSEL5_DYSC3_value << PINSEL5_2_23_bit)
# define PINSEL5_CAP3_1						(PINSEL5_CAP3_1_value << PINSEL5_2_23_bit)
# define PINSEL5_SSEL0						(PINSEL5_SSEL0_value << PINSEL5_2_23_bit)

# define PINSEL5_2_24_bit					16
# define PINSEL5_GPIO2_24_value			0
# define PINSEL5_CKEOUT0_value			1
# define PINSEL5_GPIO2_24					(PINSEL5_GPIO2_24_value	<< PINSEL5_2_24_bit)
# define PINSEL5_CKEOUT0					(PINSEL5_CKEOUT0_value	<< PINSEL5_2_24_bit)

# define PINSEL5_2_25_bit					18
# define PINSEL5_GPIO2_25_value			0
# define PINSEL5_CKEOUT1_value			1
# define PINSEL5_GPIO2_25					(PINSEL5_GPIO2_25_value << PINSEL5_2_25_bit)
# define PINSEL5_CKEOUT1					(PINSEL5_CKEOUT1_value << PINSEL5_2_25_bit)

# define PINSEL5_2_26_bit					20
# define PINSEL5_GPIO2_26_value			0
# define PINSEL5_CKEOUT2_value			1
# define PINSEL5_MAT3_0_value				2
# define PINSEL5_MISO0_value				3
# define PINSEL5_GPIO2_26					(PINSEL5_GPIO2_26_value << PINSEL5_2_26_bit)
# define PINSEL5_CKEOUT2					(PINSEL5_CKEOUT2_value << PINSEL5_2_26_bit)
# define PINSEL5_MAT3_0						(PINSEL5_MAT3_0_value << PINSEL5_2_26_bit)
# define PINSEL5_MISO0						(PINSEL5_MISO0_value << PINSEL5_2_26_bit)

# define PINSEL5_2_27_bit					22
# define PINSEL5_GPIO2_27_value			0
# define PINSEL5_CKEOUT3_value			1
# define PINSEL5_MAT3_1_value				2
# define PINSEL5_MOSI0_value				3
# define PINSEL5_GPIO2_27					(PINSEL5_GPIO2_27_value << PINSEL5_2_27_bit)
# define PINSEL5_CKEOUT3					(PINSEL5_CKEOUT3_value << PINSEL5_2_27_bit)
# define PINSEL5_MAT3_1						(PINSEL5_MAT3_1_value << PINSEL5_2_27_bit)
# define PINSEL5_MOSI0						(PINSEL5_MOSI0_value << PINSEL5_2_27_bit)

# define PINSEL5_2_28_bit					24
# define PINSEL5_GPIO2_28_value			0
# define PINSEL5_DQMOUT0_value			1
# define PINSEL5_GPIO2_28					(PINSEL5_GPIO2_28_value << PINSEL5_2_28_bit)
# define PINSEL5_DQMOUT0					(PINSEL5_DQMOUT0_value << PINSEL5_2_28_bit)

# define PINSEL5_2_29_bit					26
# define PINSEL5_GPIO2_29_value			0
# define PINSEL5_DQMOUT1_value			1
# define PINSEL5_GPIO2_29					(PINSEL5_GPIO2_29_value << PINSEL5_2_29_bit)
# define PINSEL5_DQMOUT1					(PINSEL5_DQMOUT1_value << PINSEL5_2_29_bit)

# define PINSEL5_2_30_bit					28
# define PINSEL5_GPIO2_30_value			0
# define PINSEL5_DQMOUT2_value			1
# define PINSEL5_MAT3_2_value				2
# define PINSEL5_SDA2_value				3
# define PINSEL5_GPIO2_30					(PINSEL5_GPIO2_30_value << PINSEL5_2_30_bit)
# define PINSEL5_DQMOUT2					(PINSEL5_DQMOUT2_value << PINSEL5_2_30_bit)
# define PINSEL5_MAT3_2						(PINSEL5_MAT3_2_value << PINSEL5_2_30_bit)
# define PINSEL5_SDA2						(PINSEL5_SDA2_value	<< PINSEL5_2_30_bit)

# define PINSEL5_2_31_bit					30
# define PINSEL5_GPIO2_31_value			0
# define PINSEL5_DQMOUT3_value			1
# define PINSEL5_MAT3_3_value				2
# define PINSEL5_SCL2_value				3
# define PINSEL5_GPIO2_31					(PINSEL5_GPIO2_31_value << PINSEL5_2_31_bit)
# define PINSEL5_DQMOUT3					(PINSEL5_DQMOUT3_value << PINSEL5_2_31_bit)
# define PINSEL5_MAT3_3						(PINSEL5_MAT3_3_value << PINSEL5_2_31_bit)
# define PINSEL5_SCL2						(PINSEL5_SCL2_value << PINSEL5_2_31_bit)
/*------------------------------------------------------------------------------
 PINSEL6- Pin function select registers
------------------------------------------------------------------------------*/
# define PINSEL6_3_0_bit					0
# define PINSEL6_GPIO3_0_value			0
# define PINSEL6_D0_value					1
# define PINSEL6_GPIO3_0					(PINSEL6_GPIO3_0_value << PINSEL6_3_0_bit)
# define PINSEL6_D0							(PINSEL6_D0_value << PINSEL6_3_0_bit)

# define PINSEL6_3_1_bit					2
# define PINSEL6_GPIO3_1_value			0
# define PINSEL6_D1_value					1
# define PINSEL6_GPIO3_1					(PINSEL6_GPIO3_1_value << PINSEL6_3_1_bit)
# define PINSEL6_D1							(PINSEL6_D1_value << PINSEL6_3_1_bit)

# define PINSEL6_3_2_bit					4
# define PINSEL6_GPIO3_2_value			0
# define PINSEL6_D2_value					1
# define PINSEL6_GPIO3_2					(PINSEL6_GPIO3_2_value << PINSEL6_3_2_bit)
# define PINSEL6_D2							(PINSEL6_D2_value << PINSEL6_3_2_bit)

# define PINSEL6_3_3_bit					6
# define PINSEL6_GPIO3_3_value			0
# define PINSEL6_D3_value					1
# define PINSEL6_GPIO3_3					(PINSEL6_GPIO3_3_value << PINSEL6_3_3_bit)
# define PINSEL6_D3							(PINSEL6_D3_value << PINSEL6_3_3_bit)

# define PINSEL6_3_4_bit					8
# define PINSEL6_GPIO3_4_value			0
# define PINSEL6_D4_value					1
# define PINSEL6_GPIO3_4					(PINSEL6_GPIO3_4_value << PINSEL6_3_4_bit)
# define PINSEL6_D4							(PINSEL6_D4_value << PINSEL6_3_4_bit)

# define PINSEL6_3_5_bit					10
# define PINSEL6_GPIO3_5_value			0
# define PINSEL6_D5_value					1
# define PINSEL6_GPIO3_5					(PINSEL6_GPIO3_5_value << PINSEL6_3_5_bit)
# define PINSEL6_D5							(PINSEL6_D5_value << PINSEL6_3_5_bit)

# define PINSEL6_3_6_bit					12
# define PINSEL6_GPIO3_6_value			0
# define PINSEL6_D6_value					1
# define PINSEL6_GPIO3_6					(PINSEL6_GPIO3_6_value << PINSEL6_3_6_bit)
# define PINSEL6_D6							(PINSEL6_D6_value << PINSEL6_3_6_bit)

# define PINSEL6_3_7_bit					14
# define PINSEL6_GPIO3_7_value			0
# define PINSEL6_D7_value					1
# define PINSEL6_GPIO3_7					(PINSEL6_GPIO3_7_value << PINSEL6_3_7_bit)
# define PINSEL6_D7							(PINSEL6_D7_value << PINSEL6_3_7_bit)

# define PINSEL6_3_8_bit					16
# define PINSEL6_GPIO3_8_value			0
# define PINSEL6_D8_value					1
# define PINSEL6_GPIO3_8					(PINSEL6_GPIO3_8_value << PINSEL6_3_8_bit)
# define PINSEL6_D8							(PINSEL6_D8_value << PINSEL6_3_8_bit)

# define PINSEL6_3_9_bit					18
# define PINSEL6_GPIO3_9_value			0
# define PINSEL6_D9_value					1
# define PINSEL6_GPIO3_9					(PINSEL6_GPIO3_9_value << PINSEL6_3_9_bit)
# define PINSEL6_D9							(PINSEL6_D9_value << PINSEL6_3_9_bit)

# define PINSEL6_3_10_bit					20
# define PINSEL6_GPIO3_10_value			0
# define PINSEL6_D10_value					1
# define PINSEL6_GPIO3_10					(PINSEL6_GPIO3_10_value << PINSEL6_3_10_bit)
# define PINSEL6_D10						(PINSEL6_D10_value << PINSEL6_3_10_bit)

# define PINSEL6_3_11_bit					22
# define PINSEL6_GPIO3_11_value			0
# define PINSEL6_D11_value					1
# define PINSEL6_GPIO3_11					(PINSEL6_GPIO3_11_value << PINSEL6_3_11_bit)
# define PINSEL6_D11						(PINSEL6_D11_value << PINSEL6_3_11_bit)

# define PINSEL6_3_12_bit					24
# define PINSEL6_GPIO3_12_value			0
# define PINSEL6_D12_value					1
# define PINSEL6_GPIO3_12					(PINSEL6_GPIO3_12_value << PINSEL6_3_12_bit)
# define PINSEL6_D12						(PINSEL6_D12_value << PINSEL6_3_12_bit)

# define PINSEL6_3_13_bit					26
# define PINSEL6_GPIO3_13_value			0
# define PINSEL6_D13_value					1
# define PINSEL6_GPIO3_13					(PINSEL6_GPIO3_13_value << PINSEL6_3_13_bit)
# define PINSEL6_D13						(PINSEL6_D13_value << PINSEL6_3_13_bit)

# define PINSEL6_3_14_bit					28
# define PINSEL6_GPIO3_14_value			0
# define PINSEL6_D14_value					1
# define PINSEL6_GPIO3_14					(PINSEL6_GPIO3_14_value << PINSEL6_3_14_bit)
# define PINSEL6_D14						(PINSEL6_D14_value << PINSEL6_3_14_bit)

# define PINSEL6_3_15_bit					30
# define PINSEL6_GPIO3_15_value			0
# define PINSEL6_D15_value					1
# define PINSEL6_GPIO3_15					(PINSEL6_GPIO3_15_value << PINSEL6_3_15_bit)
# define PINSEL6_D15						(PINSEL6_D15_value << PINSEL6_3_15_bit)

/*------------------------------------------------------------------------------
 PINSEL7- Pin function select registers
------------------------------------------------------------------------------*/
# define PINSEL7_3_16_bit					0
# define PINSEL7_GPIO3_16_value			0
# define PINSEL7_D16_value					1
# define PINSEL7_PWM0_1_value				2
# define PINSEL7_TXD1_value				3
# define PINSEL7_GPIO3_16					(PINSEL7_GPIO3_16_value << PINSEL7_3_16_bit)
# define PINSEL7_D16							(PINSEL7_D16_value << PINSEL7_3_16_bit)
# define PINSEL7_PWM0_1						(PINSEL7_PWM0_1_value << PINSEL7_3_16_bit)
# define PINSEL7_TXD1						(PINSEL7_TXD1_value << PINSEL7_3_16_bit)

# define PINSEL7_3_17_bit					2
# define PINSEL7_GPIO3_17_value			0
# define PINSEL7_D17_value					1
# define PINSEL7_PWM0_2_value				2
# define PINSEL7_RXD1_value				3
# define PINSEL7_GPIO3_17					(PINSEL7_GPIO3_17_value << PINSEL7_3_17_bit)
# define PINSEL7_D17							(PINSEL7_D17_value << PINSEL7_3_17_bit)
# define PINSEL7_PWM0_2						(PINSEL7_PWM0_2_value << PINSEL7_3_17_bit)
# define PINSEL7_RXD1						(PINSEL7_RXD1_value << PINSEL7_3_17_bit)

# define PINSEL7_3_18_bit					4
# define PINSEL7_GPIO3_18_value			0
# define PINSEL7_D18_value					1
# define PINSEL7_PWM0_3_value				2
# define PINSEL7_CTS1_value				3
# define PINSEL7_GPIO3_18					(PINSEL7_GPIO3_18_value << PINSEL7_3_18_bit)
# define PINSEL7_D18							(PINSEL7_D18_value << PINSEL7_3_18_bit)
# define PINSEL7_PWM0_3						(PINSEL7_PWM0_3_value << PINSEL7_3_18_bit)
# define PINSEL7_CTS1						(PINSEL7_CTS1_value << PINSEL7_3_18_bit)

# define PINSEL7_3_19_bit					6
# define PINSEL7_GPIO3_19_value			0
# define PINSEL7_D19_value					1
# define PINSEL7_PWM0_4_value				2
# define PINSEL7_DCD1_value				3
# define PINSEL7_GPIO3_19					(PINSEL7_GPIO3_19_value << PINSEL7_3_19_bit)
# define PINSEL7_D19							(PINSEL7_D19_value << PINSEL7_3_19_bit)
# define PINSEL7_PWM0_4						(INSEL7_PWM0_4_value << PINSEL7_3_19_bit)
# define PINSEL7_DCD1						(PINSEL7_DCD1_value << PINSEL7_3_19_bit)

# define PINSEL7_3_20_bit					8
# define PINSEL7_GPIO3_20_value			0
# define PINSEL7_D20_value					1
# define PINSEL7_PWM0_5_value				2
# define PINSEL7_DSR1_value				3
# define PINSEL7_GPIO3_20					(PINSEL7_GPIO3_20_value	<< PINSEL7_3_20_bit)
# define PINSEL7_D20							(PINSEL7_D20_value << PINSEL7_3_20_bit)
# define PINSEL7_PWM0_5						(PINSEL7_PWM0_5_value << PINSEL7_3_20_bit)
# define PINSEL7_DSR1						(PINSEL7_DSR1_value  << PINSEL7_3_20_bit)

# define PINSEL7_3_21_bit					10
# define PINSEL7_GPIO3_21_value			0
# define PINSEL7_D21_value					1
# define PINSEL7_PWM0_6_value				2
# define PINSEL7_DR1_value					3
# define PINSEL7_GPIO3_21					(PINSEL7_GPIO3_21_value << PINSEL7_3_21_bit)
# define PINSEL7_D21							(PINSEL7_D21_value << PINSEL7_3_21_bit)
# define PINSEL7_PWM0_6						(PINSEL7_PWM0_6_value << PINSEL7_3_21_bit)
# define PINSEL7_DR1							(PINSEL7_DR1_value<< PINSEL7_3_21_bit)

# define PINSEL7_3_22_bit					12
# define PINSEL7_GPIO3_22_value			0
# define PINSEL7_D22_value					1
# define PINSEL7_PCAP0_0_value			2
# define PINSEL7_RI1_value					3
# define PINSEL7_GPIO3_22					(PINSEL7_GPIO3_22_value << PINSEL7_3_22_bit)
# define PINSEL7_D22							(PINSEL7_D22_value << PINSEL7_3_22_bit)
# define PINSEL7_PCAP0_0					(PINSEL7_PCAP0_0_value << PINSEL7_3_22_bit)
# define PINSEL7_RI1							(PINSEL7_RI1_value << PINSEL7_3_22_bit)

# define PINSEL7_3_23_bit					14
# define PINSEL7_GPIO3_23_value			0
# define PINSEL7_D23_value					1
# define PINSEL7_CAP0_0_value				2
# define PINSEL7_PCAP1_0_value			3
# define PINSEL7_GPIO3_23					(INSEL7_GPIO3_23_value << PINSEL7_3_23_bit)
# define PINSEL7_D23							(PINSEL7_D23_value << PINSEL7_3_23_bit)
# define PINSEL7_CAP0_0						(PINSEL7_CAP0_0_value << PINSEL7_3_23_bit)
# define PINSEL7_PCAP1_0					(PINSEL7_PCAP1_0_value << PINSEL7_3_23_bit)

# define PINSEL7_3_24_bit					16
# define PINSEL7_GPIO3_24_value			0
# define PINSEL7_D24_value					1
# define PINSEL7_CAP0_1_value				2
# define PINSEL7_PWM1_1_value				3
# define PINSEL7_GPIO3_24					(PINSEL7_GPIO3_24_value << PINSEL7_3_24_bit)
# define PINSEL7_D24							(PINSEL7_D24_value << PINSEL7_3_24_bit)
# define PINSEL7_CAP0_1						(PINSEL7_CAP0_1_value << PINSEL7_3_24_bit)
# define PINSEL7_PWM1_1						(PINSEL7_PWM1_1_value << PINSEL7_3_24_bit)

# define PINSEL7_3_25_bit					18
# define PINSEL7_GPIO3_25_value			0
# define PINSEL7_D25_value					1
# define PINSEL7_MAT0_0_value				2
# define PINSEL7_PWM1_2_value				3
# define PINSEL7_GPIO3_25					(PINSEL7_GPIO3_25_value << PINSEL7_3_25_bit)
# define PINSEL7_D25							(PINSEL7_D25_value << PINSEL7_3_25_bit)
# define PINSEL7_MAT0_0						(PINSEL7_MAT0_0_value << PINSEL7_3_25_bit)
# define PINSEL7_PWM1_2						(PINSEL7_PWM1_2_value << PINSEL7_3_25_bit)

# define PINSEL7_3_26_bit					20
# define PINSEL7_GPIO3_26_value			0
# define PINSEL7_D26_value					1
# define PINSEL7_MAT0_1_value				2
# define PINSEL7_PWM1_3_value				3
# define PINSEL7_GPIO3_26					(PINSEL7_GPIO3_26_value << PINSEL7_3_26_bit)
# define PINSEL7_D26							(PINSEL7_D26_value << PINSEL7_3_26_bit)
# define PINSEL7_MAT0_1						(PINSEL7_MAT0_1_value << PINSEL7_3_26_bit)
# define PINSEL7_PWM1_3						(PINSEL7_PWM1_3_value << PINSEL7_3_26_bit)

# define PINSEL7_3_27_bit					22
# define PINSEL7_GPIO3_27_value			0
# define PINSEL7_D27_value					1
# define PINSEL7_CAP1_0_value				2
# define PINSEL7_PWM1_4_value				3
# define PINSEL7_GPIO3_27					(PINSEL7_GPIO3_27_value << PINSEL7_3_27_bit)
# define PINSEL7_D27							(PINSEL7_D27_value << PINSEL7_3_27_bit)
# define PINSEL7_CAP1_0						(PINSEL7_CAP1_0_value << PINSEL7_3_27_bit)
# define PINSEL7_PWM1_4						(PINSEL7_PWM1_4_value << PINSEL7_3_27_bit)

# define PINSEL7_3_28_bit					24
# define PINSEL7_GPIO3_28_value			0
# define PINSEL7_D28_value					1
# define PINSEL7_CAP1_1_value				2
# define PINSEL7_PWM1_5_value				3
# define PINSEL7_GPIO3_28					(PINSEL7_GPIO3_28_value << PINSEL7_3_28_bit)
# define PINSEL7_D28							(PINSEL7_D28_value << PINSEL7_3_28_bit)
# define PINSEL7_CAP1_1						(PINSEL7_CAP1_1_value << PINSEL7_3_28_bit)
# define PINSEL7_PWM1_5						(PINSEL7_PWM1_5_value << PINSEL7_3_28_bit)

# define PINSEL7_3_29_bit					26
# define PINSEL7_GPIO3_29_value			0
# define PINSEL7_D29_value					1
# define PINSEL7_MAT1_0_value				2
# define PINSEL7_PWM1_6_value				3
# define PINSEL7_GPIO3_29					(PINSEL7_GPIO3_29_value << PINSEL7_3_29_bit)
# define PINSEL7_D29							(PINSEL7_D29_value << PINSEL7_3_29_bit)
# define PINSEL7_MAT1_0						(PINSEL7_MAT1_0_value << PINSEL7_3_29_bit)
# define PINSEL7_PWM1_6						(PINSEL7_PWM1_6_value << PINSEL7_3_29_bit)

# define PINSEL7_3_30_bit					28
# define PINSEL7_GPIO3_30_value			0
# define PINSEL7_D30_value					1
# define PINSEL7_MAT1_1_value				2
# define PINSEL7_RTS1_value				3
# define PINSEL7_GPIO3_30					(PINSEL7_GPIO3_30_value << PINSEL7_3_30_bit)
# define PINSEL7_D30							(PINSEL7_D30_value << PINSEL7_3_30_bit)
# define PINSEL7_MAT1_1						(PINSEL7_MAT1_1_value << PINSEL7_3_30_bit)
# define PINSEL7_RTS1						(PINSEL7_RTS1_value << PINSEL7_3_30_bit)

# define PINSEL7_3_31_bit					30
# define PINSEL7_GPIO3_31_value			0
# define PINSEL7_D31_value					1
# define PINSEL7_MAT1_2_value				2
# define PINSEL7_GPIO3_31					(PINSEL7_GPIO3_31_value << PINSEL7_3_31_bit)
# define PINSEL7_D31							(PINSEL7_D31_value << PINSEL7_3_31_bit)
# define PINSEL7_MAT1_2						(PINSEL7_MAT1_2_value << PINSEL7_3_31_bit)

/*------------------------------------------------------------------------------
 PINSEL8- Pin function select registers
------------------------------------------------------------------------------*/
# define PINSEL8_4_0_bit					0
# define PINSEL8_GPIO4_0_value			0
# define PINSEL8_A0_value					1
# define PINSEL8_GPIO4_0					(PINSEL8_GPIO4_0_value << PINSEL8_4_0_bit)
# define PINSEL8_A0							(PINSEL8_A0_value << PINSEL8_4_0_bit)

# define PINSEL8_4_1_bit					2
# define PINSEL8_GPIO4_1_value			0
# define PINSEL8_A1_value					1
# define PINSEL8_GPIO4_1					(PINSEL8_GPIO4_1_value << PINSEL8_4_1_bit)
# define PINSEL8_A1							(PINSEL8_A1_value << PINSEL8_4_1_bit)

# define PINSEL8_4_2_bit					4
# define PINSEL8_GPIO4_2_value			0
# define PINSEL8_A2_value					1
# define PINSEL8_GPIO4_2					(PINSEL8_GPIO4_2_value << PINSEL8_4_2_bit)
# define PINSEL8_A2							(PINSEL8_A2_value << PINSEL8_4_2_bit)

# define PINSEL8_4_3_bit					6
# define PINSEL8_GPIO4_3_value			0
# define PINSEL8_A3_value					1
# define PINSEL8_GPIO4_3					(PINSEL8_GPIO4_3_value << PINSEL8_4_3_bit)
# define PINSEL8_A3							(PINSEL8_A3_value << PINSEL8_4_3_bit)

# define PINSEL8_4_4_bit					8
# define PINSEL8_GPIO4_4_value			0
# define PINSEL8_A4_value					1
# define PINSEL8_GPIO4_4					(PINSEL8_GPIO4_4_value << PINSEL8_4_4_bit)
# define PINSEL8_A4							(PINSEL8_A4_value << PINSEL8_4_4_bit)

# define PINSEL8_4_5_bit					10
# define PINSEL8_GPIO4_5_value			0
# define PINSEL8_A5_value					1
# define PINSEL8_GPIO4_5					(PINSEL8_GPIO4_5_value << PINSEL8_4_5_bit)
# define PINSEL8_A5							(PINSEL8_A5_value << PINSEL8_4_5_bit)

# define PINSEL8_4_6_bit					12
# define PINSEL8_GPIO4_6_value			0
# define PINSEL8_A6_value					1
# define PINSEL8_GPIO4_6					(PINSEL8_GPIO4_6_value << PINSEL8_4_6_bit)
# define PINSEL8_A6							(PINSEL8_A6_value << PINSEL8_4_6_bit)

# define PINSEL8_4_7_bit					14
# define PINSEL8_GPIO4_7_value			0
# define PINSEL8_A7_value					1
# define PINSEL8_GPIO4_7					(PINSEL8_GPIO4_7_value << PINSEL8_4_7_bit)
# define PINSEL8_A7							(PINSEL8_A7_value << PINSEL8_4_7_bit)

# define PINSEL8_4_8_bit					16
# define PINSEL8_GPIO4_8_value			0
# define PINSEL8_A8_value					1
# define PINSEL8_GPIO4_8					(PINSEL8_GPIO4_8_value << PINSEL8_4_8_bit)
# define PINSEL8_A8							(PINSEL8_A8_value << PINSEL8_4_8_bit)

# define PINSEL8_4_9_bit					18
# define PINSEL8_GPIO4_9_value			0
# define PINSEL8_A9_value					1
# define PINSEL8_GPIO4_9					(PINSEL8_GPIO4_9_value << PINSEL8_4_9_bit)
# define PINSEL8_A9							(PINSEL8_A9_value << PINSEL8_4_9_bit)

# define PINSEL8_4_10_bit					20
# define PINSEL8_GPIO4_10_value			0
# define PINSEL8_A10_value					1
# define PINSEL8_GPIO4_10					(PINSEL8_GPIO4_10_value << PINSEL8_4_10_bit)
# define PINSEL8_A10							(PINSEL8_A10_value << PINSEL8_4_10_bit)

# define PINSEL8_4_11_bit					22
# define PINSEL8_GPIO4_11_value			0
# define PINSEL8_A11_value					1
# define PINSEL8_GPIO4_11					(PINSEL8_GPIO4_11_value << PINSEL8_4_11_bit)
# define PINSEL8_A11							(PINSEL8_A11_value << PINSEL8_4_11_bit)

# define PINSEL8_4_12_bit					24
# define PINSEL8_GPIO4_12_value			0
# define PINSEL8_A12_value					1
# define PINSEL8_GPIO4_12					(PINSEL8_GPIO4_12_value << PINSEL8_4_12_bit)
# define PINSEL8_A12							(PINSEL8_A12_value << PINSEL8_4_12_bit)

# define PINSEL8_4_13_bit					26
# define PINSEL8_GPIO4_13_value			0
# define PINSEL8_A13_value					1
# define PINSEL8_GPIO4_13					(PINSEL8_GPIO4_13_value << PINSEL8_4_13_bit)
# define PINSEL8_A13							(PINSEL8_A13_value << PINSEL8_4_13_bit)

# define PINSEL8_4_14_bit					28
# define PINSEL8_GPIO4_14_value			0
# define PINSEL8_A14_value					1
# define PINSEL8_GPIO4_14					(PINSEL8_GPIO4_14_value << PINSEL8_4_14_bit)
# define PINSEL8_A14							(PINSEL8_A14_value << PINSEL8_4_14_bit)

# define PINSEL8_4_15_bit					30
# define PINSEL8_GPIO4_15_value			0
# define PINSEL8_A15_value					1
# define PINSEL8_GPIO4_15					(PINSEL8_GPIO4_15_value << PINSEL8_4_15_bit)
# define PINSEL8_A15							(PINSEL8_A15_value << PINSEL8_4_15_bit)

/*------------------------------------------------------------------------------
 PINSEL9- Pin function select registers
------------------------------------------------------------------------------*/
# define PINSEL9_4_16_bit					0
# define PINSEL9_GPIO4_16_value			0
# define PINSEL9_A16_value					1
# define PINSEL9_GPIO4_16					(PINSEL9_GPIO4_16_value << PINSEL9_4_16_bit)
# define PINSEL9_A16							(PINSEL9_A16_value << PINSEL9_4_16_bit)

# define PINSEL9_4_17_bit					2
# define PINSEL9_GPIO4_17_value			0
# define PINSEL9_A17_value					1
# define PINSEL9_GPIO4_17					(PINSEL9_GPIO4_17_value << PINSEL9_4_17_bit)
# define PINSEL9_A17							(PINSEL9_A17_value << PINSEL9_4_17_bit)

# define PINSEL9_4_18_bit					4
# define PINSEL9_GPIO4_18_value			0
# define PINSEL9_A18_value					1
# define PINSEL9_GPIO4_18					(PINSEL9_GPIO4_18_value << PINSEL9_4_18_bit)
# define PINSEL9_A18							(PINSEL9_A18_value << PINSEL9_4_18_bit)

# define PINSEL9_4_19_bit					6
# define PINSEL9_GPIO4_19_value			0
# define PINSEL9_A19_value					1
# define PINSEL9_GPIO4_19					(PINSEL9_GPIO4_19_value << PINSEL9_4_19_bit)
# define PINSEL9_A19							(PINSEL9_A19_value << PINSEL9_4_19_bit)

# define PINSEL9_4_20_bit					8
# define PINSEL9_GPIO4_20_value			0
# define PINSEL9_A20_value					1
# define PINSEL9_SDA2_value				2
# define PINSEL9_SCK1_value				3
# define PINSEL9_GPIO4_20					(PINSEL9_GPIO4_20_value	<< PINSEL9_4_20_bit)
# define PINSEL9_A20							(PINSEL9_A20_value	<< PINSEL9_4_20_bit)
# define PINSEL9_SDA2						(PINSEL9_SDA2_value << PINSEL9_4_20_bit)
# define PINSEL9_SCK1						(PINSEL9_SCK1_value << PINSEL9_4_20_bit)

# define PINSEL9_4_21_bit					10
# define PINSEL9_GPIO4_21_value			0
# define PINSEL9_A21_value					1
# define PINSEL9_SCL2_value				2
# define PINSEL9_SSEL1_value				3
# define PINSEL9_GPIO4_21					(PINSEL9_GPIO4_21_value << PINSEL9_4_21_bit)
# define PINSEL9_A21							(PINSEL9_A21_value << PINSEL9_4_21_bit)
# define PINSEL9_SCL2						(PINSEL9_SCL2_value << PINSEL9_4_21_bit)
# define PINSEL9_SSEL1						(PINSEL9_SSEL1_value << PINSEL9_4_21_bit)

# define PINSEL9_4_22_bit					12
# define PINSEL9_GPIO4_22_value			0
# define PINSEL9_A22_value					1
# define PINSEL9_TXD2_value				2
# define PINSEL9_MISO1_value				3
# define PINSEL9_GPIO4_22					(PINSEL9_GPIO4_22_value << PINSEL9_4_22_bit)
# define PINSEL9_A22							(PINSEL9_A22_value << PINSEL9_4_22_bit)
# define PINSEL9_TXD2						(PINSEL9_TXD2_value << PINSEL9_4_22_bit)
# define PINSEL9_MISO1						(PINSEL9_MISO1_value << PINSEL9_4_22_bit)

# define PINSEL9_4_23_bit					14
# define PINSEL9_GPIO4_23_value			0
# define PINSEL9_A23_value					1
# define PINSEL9_RXD2_value				2
# define PINSEL9_MOSI1_value				3
# define PINSEL9_GPIO4_23					(PINSEL9_GPIO4_23_value << PINSEL9_4_23_bit)
# define PINSEL9_A23							(PINSEL9_A23_value << PINSEL9_4_23_bit)
# define PINSEL9_RXD2						(PINSEL9_RXD2_value << PINSEL9_4_23_bit)
# define PINSEL9_MOSI1						(PINSEL9_MOSI1_value << PINSEL9_4_23_bit)

# define PINSEL9_4_24_bit					16
# define PINSEL9_GPIO4_24_value			0
# define PINSEL9_OE_value					1
# define PINSEL9_GPIO4_24					(PINSEL9_GPIO4_24_value << PINSEL9_4_24_bit)
# define PINSEL9_OE							(PINSEL9_OE_value << PINSEL9_4_24_bit)

# define PINSEL9_4_25_bit					18
# define PINSEL9_GPIO4_25_value			0
# define PINSEL9_WE_value					1
# define PINSEL9_GPIO4_25					(PINSEL9_GPIO4_25_value << PINSEL9_4_25_bit)
# define PINSEL9_WE							(PINSEL9_WE_value << PINSEL9_4_25_bit)

# define PINSEL9_4_26_bit					20
# define PINSEL9_GPIO4_26_value			0
# define PINSEL9_BLS0_value				1
# define PINSEL9_GPIO4_26					(PINSEL9_GPIO4_26_value << PINSEL9_4_26_bit)
# define PINSEL9_BLS0						(PINSEL9_BLS0_value << PINSEL9_4_26_bit)

# define PINSEL9_4_27_bit					22
# define PINSEL9_GPIO4_27_value			0
# define PINSEL9_BLS1_value				1
# define PINSEL9_GPIO4_27					(PINSEL9_GPIO4_27_value << PINSEL9_4_27_bit)
# define PINSEL9_BLS1						(PINSEL9_BLS1_value << PINSEL9_4_27_bit)

# define PINSEL9_4_28_bit					24
# define PINSEL9_GPIO4_28_value			0
# define PINSEL9_BLS2_value				1
# define PINSEL9_MAT2_0_value				2
# define PINSEL9_TXD3_value				3
# define PINSEL9_GPIO4_28					(PINSEL9_GPIO4_28_value << PINSEL9_4_28_bit)
# define PINSEL9_BLS2						(PINSEL9_BLS2_value << PINSEL9_4_28_bit)
# define PINSEL9_MAT2_0						(PINSEL9_MAT2_0_value << PINSEL9_4_28_bit)
# define PINSEL9_TXD3						(PINSEL9_TXD3_value	 << PINSEL9_4_28_bit)

# define PINSEL9_4_29_bit					26
# define PINSEL9_GPIO4_29_value			0
# define PINSEL9_BLS3_value				1
# define PINSEL9_MAT2_1_value				2
# define PINSEL9_RXD3_value				3
# define PINSEL9_GPIO4_29					(PINSEL9_GPIO4_29_value	<< PINSEL9_4_29_bit)
# define PINSEL9_BLS3						(PINSEL9_BLS3_value << PINSEL9_4_29_bit)
# define PINSEL9_MAT2_1						(PINSEL9_MAT2_1_value << PINSEL9_4_29_bit)
# define PINSEL9_RXD3						(PINSEL9_RXD3_value << PINSEL9_4_29_bit)

# define PINSEL9_4_30_bit					28
# define PINSEL9_GPIO4_30_value			0
# define PINSEL9_CS0_value					1
# define PINSEL9_GPIO4_30					(PINSEL9_GPIO4_30_value << PINSEL9_4_30_bit)
# define PINSEL9_CS0							(PINSEL9_CS0_value << PINSEL9_4_30_bit)

# define PINSEL9_4_31_bit					30
# define PINSEL9_GPIO4_31_value			0
# define PINSEL9_CS1_value					1
# define PINSEL9_GPIO4_31					(PINSEL9_GPIO4_31_value	<< PINSEL9_4_31_bit)
# define PINSEL9_CS1							(PINSEL9_CS1_value	<< PINSEL9_4_31_bit)

/*------------------------------------------------------------------------------
 PINSEL10- Pin function select registers
------------------------------------------------------------------------------*/
# define PINSEL10_ETM_bit					3
# define PINSEL10_ETM						(1 << PINSEL10_ETM_bit)

/*------------------------------------------------------------------------------
 PINSEL11- Pin function select registers
------------------------------------------------------------------------------*/
# define PINSEL11_LCDPE_bit					0
# define PINSEL11_LCDM_bit						1
# define PINSEL11_LCDM_4B_STN_SP_value		0		/* 4 bit mono STN single panel */
# define PINSEL11_LCDM_8B_STN_SP_value		1		/* 8 bit mono STN single panel or color STN single panel */
# define PINSEL11_LCDM_4B_STN_DP_value		2		/* 4 bit mono STN dual panel */
# define PINSEL11_LCDM_COLOR_STN_DP_value	3		/* color STN dual panel or 8 bit mono STN dual panel */
# define PINSEL11_LCDM_12B_TFT_value		4		/* 12 bit TFT (4:4:4 mode) */
# define PINSEL11_LCDM_16B_TFT_value		5		/* 16 bit TFT (5:6:5 mode) */
# define PINSEL11_LCDM_16B_TFT2_value		6		/* 16 bit TFT (1:5:5:5 mode) */
# define PINSEL11_LCDM_24B_TFT_value		7		/* 24 bit TFT */
# define PINSEL11_LCDPE							(1 << PINSEL11_LCDPE_bit)
# define PINSEL11_LCDM_4B_STN_SP				(PINSEL11_LCDM_4B_STN_SP_value << PINSEL11_LCDM_bit)
# define PINSEL11_LCDM_8B_STN_SP				(PINSEL11_LCDM_8B_STN_SP_value << PINSEL11_LCDM_bit)
# define PINSEL11_LCDM_4B_STN_DP				(PINSEL11_LCDM_4B_STN_DP_value << PINSEL11_LCDM_bit)
# define PINSEL11_LCDM_COLOR_STN_DP			(PINSEL11_LCDM_COLOR_STN_DP_value << PINSEL11_LCDM_bit)
# define PINSEL11_LCDM_12B_TFT				(PINSEL11_LCDM_12B_TFT_value << PINSEL11_LCDM_bit)
# define PINSEL11_LCDM_16B_TFT				(PINSEL11_LCDM_16B_TFT_value << PINSEL11_LCDM_bit)
# define PINSEL11_LCDM_16B_TFT2				(PINSEL11_LCDM_16B_TFT2_value << PINSEL11_LCDM_bit)
# define PINSEL11_LCDM_24B_TFT				(PINSEL11_LCDM_24B_TFT_value << PINSEL11_LCDM_bit)

/*------------------------------------------------------------------------------
 SSP
------------------------------------------------------------------------------*/
/* SSPxCR0 - SSPx Control Register */
# define SSP_CR0_DSS_bit						0
# define SSP_CR0_FRF_bit						4
# define SSP_CR0_CPOL_bit						6
# define SSP_CR0_CPHA_bit						7
# define SSP_CR0_SCR_bit						8

# define SSP_CR0_DSS_4BIT_value				0x3
# define SSP_CR0_DSS_5BIT_value				0x4
# define SSP_CR0_DSS_6BIT_value				0x5
# define SSP_CR0_DSS_7BIT_value				0x6
# define SSP_CR0_DSS_8BIT_value				0x7
# define SSP_CR0_DSS_9BIT_value				0x8
# define SSP_CR0_DSS_10BIT_value				0x9
# define SSP_CR0_DSS_11BIT_value				0xA
# define SSP_CR0_DSS_12BIT_value				0xB
# define SSP_CR0_DSS_13BIT_value				0xC
# define SSP_CR0_DSS_14BIT_value				0xD
# define SSP_CR0_DSS_15BIT_value				0xE
# define SSP_CR0_DSS_16BIT_value				0xF

# define SSP_CR0_FRF_SPI_value				0
# define SSP_CR0_FRF_TI_value					0x1
# define SSP_CR0_FRF_MICROWIRE_value		0x2

# define SSP_CR0_SCR_value						0x5

# define SSP_CR0_DSS_4BIT						(SSP_CR0_DSS_4BIT_value << SSP_CR0_DSS_bit)
# define SSP_CR0_DSS_5BIT						(SSP_CR0_DSS_5BIT_value << SSP_CR0_DSS_bit)
# define SSP_CR0_DSS_6BIT						(SSP_CR0_DSS_6BIT_value << SSP_CR0_DSS_bit)
# define SSP_CR0_DSS_7BIT						(SSP_CR0_DSS_7BIT_value << SSP_CR0_DSS_bit)
# define SSP_CR0_DSS_8BIT						(SSP_CR0_DSS_8BIT_value << SSP_CR0_DSS_bit)
# define SSP_CR0_DSS_9BIT						(SSP_CR0_DSS_9BIT_value << SSP_CR0_DSS_bit)
# define SSP_CR0_DSS_10BIT						(SSP_CR0_DSS_10BIT_value << SSP_CR0_DSS_bit)
# define SSP_CR0_DSS_11BIT						(SSP_CR0_DSS_11BIT_value << SSP_CR0_DSS_bit)
# define SSP_CR0_DSS_12BIT						(SSP_CR0_DSS_12BIT_value << SSP_CR0_DSS_bit)
# define SSP_CR0_DSS_13BIT						(SSP_CR0_DSS_13BIT_value << SSP_CR0_DSS_bit)
# define SSP_CR0_DSS_14BIT						(SSP_CR0_DSS_14BIT_value << SSP_CR0_DSS_bit)
# define SSP_CR0_DSS_15BIT						(SSP_CR0_DSS_15BIT_value << SSP_CR0_DSS_bit)
# define SSP_CR0_DSS_16BIT						(SSP_CR0_DSS_16BIT_value << SSP_CR0_DSS_bit)
# define SSP_CR0_FRF_SPI						(SSP_CR0_FRF_SPI_value << SSP_CR0_FRF_bit)
# define SSP_CR0_FRF_TI							(SSP_CR0_FRF_TI_value << SSP_CR0_FRF_bit)
# define SSP_CR0_FRF_MICROWIRE				(SSP_CR0_FRF_MICROWIRE_value << SSP_CR0_FRF_bit)
# define SSP_CR0_CPOL							(1 << SSP_CR0_CPOL_bit)
# define SSP_CR0_CPHA							(1 << SSP_CR0_CPHA_bit)
# define SSP_CR0_SCR								(SSP_CR0_SCR_value << SSP_CR0_SCR_bit)

/* SSP0CR1 - SSP0 Control Register 1 */
# define SSP_CR1_LBM_bit						0
# define SSP_CR1_SSE_bit						1
# define SSP_CR1_MS_bit							2
# define SSP_CR1_SOD_bit						3

# define SSP_CR1_LBM								(1 << SSP_CR1_LBM_bit)
# define SSP_CR1_SSE								(1 << SSP_CR1_SSE_bit)
# define SSP_CR1_MS								(1 << SSP_CR1_MS_bit)
# define SSP_CR1_SOD								(1 << SSP_CR1_SOD_bit)

/* SSP0DR -SSP0 Data Register */
# define SSP_DR_DATA_mask						0xFFFF

/* SSP0SR - SSP0 Status Register */
# define SSP_SR_TFE_bit							0
# define SSP_SR_TNF_bit							1
# define SSP_SR_RNE_bit							2
# define SSP_SR_RFF_bit							3
# define SSP_SR_BSY_bit							4

# define SSP_SR_TFE								(1 << SSP_SR_TFE_bit)
# define SSP_SR_TNF								(1 << SSP_SR_TNF_bit)
# define SSP_SR_RNE								(1 << SSP_SR_RNE_bit)
# define SSP_SR_RFF								(1 << SSP_SR_RFF_bit)
# define SSP_SR_BSY								(1 << SSP_SR_BSY_bit)

/* SSP0CPSR - SSP0 Clock Prescale Reigster */
# define SSP_CPSR_CPSDVSR_mask				0xFF

/* SSP0IMSC - SSP0 Interrupt Mask Set/Clear Register */
# define SSP_IMSC_RORIM_bit					0
# define SSP_IMSC_RTIM_bit						1
# define SSP_IMSC_RXIM_bit						2
# define SSP_IMSC_TXIM_bit						3

# define SSP_IMSC_RORIM							(1 << SSP_IMSC_RORIM_bit)
# define SSP_IMSC_RTIM							(1 << SSP_IMSC_RTIM_bit)
# define SSP_IMSC_RXIM							(1 << SSP_IMSC_RXIM_bit)
# define SSP_IMSC_TXIM							(1 << SSP_IMSC_TXIM_bit)

/* SSP0MIS - SSP0 Masked Interrupt Status */
# define SSP_MIS_RORMIS_bit					0
# define SSP_MIS_RTMIS_bit						1
# define SSP_MIS_RXMIS_bit						2
# define SSP_MIS_TXMIS_bit						3

# define SSP_MIS_RORMIS							(1 << SSP_MIS_RORMIS_bit)
# define SSP_MIS_RTMIS							(1 << SSP_MIS_RTMIS_bit)
# define SSP_MIS_RXMIS							(1 << SSP_MIS_RXMIS_bit)
# define SSP_MIS_TXMIS							(1 << SSP_MIS_TXMIS_bit)

/* SSP0ICR - SSP0 Interrupt Clear Register */
# define SSP_ICR_RORIC_bit						0
# define SSP_ICR_RTIC_bit						1

# define SSP_ICR_RORIC							(1 << SSP_ICR_RORIC_bit)
# define SSP_ICR_RTIC							(1 << SSP_ICR_RTIC_bit)

/* SSP0DMACR - SSP0 DMA Control Register */
# define SSP_DMACR_RXDMAE_bit					0
# define SSP_DMACR_TXDMAE_bit					1

# define SSP_DMACR_RXDMAE						(1 << SSP_DMACR_RXDMAE_bit)
# define SSP_DMACR_TXDMAE						(1 << SSP_DMACR_TXDMAE_bit)

/*------------------------------------------------------------------------------
 ADC
------------------------------------------------------------------------------*/
/*------------------------------------------------------------------------------
 CAN
------------------------------------------------------------------------------*/
/*------------------------------------------------------------------------------
 DAC
------------------------------------------------------------------------------*/
/*------------------------------------------------------------------------------
 SD/MMC Card Interface
------------------------------------------------------------------------------*/
# define MCI_POWER_CTRL_bit					0
# define MCI_POWER_OPEN_DRAIN_bit			6
# define MCI_POWER_ROD_bit						7
# define MCI_POWER_CTRL_POWEROFF_value		0
# define MCI_POWER_CTRL_POWERUP_value		2
# define MCI_POWER_CTRL_POWERON_value		3
# define MCI_POWER_CTRL_POWEROFF				(MCI_POWER_CTRL_POWEROFF_value << MCI_POWER_CTRL_bit)
# define MCI_POWER_CTRL_POWERUP				(MCI_POWER_CTRL_POWERUP_value << MCI_POWER_CTRL_bit)
# define MCI_POWER_CTRL_POWERON				(MCI_POWER_CTRL_POWERON_value << MCI_POWER_CTRL_bit)
# define MCI_POWER_OPEN_DRAIN					(1 << MCI_POWER_OPEN_DRAIN_bit)
# define MCI_POWER_ROD							(1 << MCI_POWER_ROD_bit)

# define MCI_CLOCK_CLK_DIV_bit				0
# define MCI_CLOCK_ENABLE_bit					8
# define MCI_CLOCK_PWR_SAVE_bit 				9
# define MCI_CLOCK_BYPASS_bit					10
# define MCI_CLOCK_WIDE_BUS_bit				11
# define MCI_CLOCK_CLK_DIV_value				0
# define MCI_CLOCK_ENABLE						(1 << MCI_CLOCK_ENABLE_bit)
# define MCI_CLOCK_PWR_SAVE 					(1 << MCI_CLOCK_PWR_SAVE_bit)
# define MCI_CLOCK_BYPASS						(1 << MCI_CLOCK_BYPASS_bit)
# define MCI_CLOCK_WIDE_BUS					(1 << MCI_CLOCK_WIDE_BUS_bit)

# define MCI_COMMAND_CMD_INDEX_bit			0
# define MCI_COMMAND_CMD_INDEX_mask			0x3F
# define MCI_COMMAND_RESPONSE_bit			6
# define MCI_COMMAND_LONG_RSP_bit			7
# define MCI_COMMAND_INTERRUPT_bit			8
# define MCI_COMMAND_PENDING_bit				9
# define MCI_COMMAND_CPSM_ENABLE_bit		10
# define MCI_COMMAND_CMD_INDEX				(1 << MCI_COMMAND_CMD_INDEX_bit)
# define MCI_COMMAND_RESPONSE					(1 << MCI_COMMAND_RESPONSE_bit)
# define MCI_COMMAND_LONG_RSP					(1 << MCI_COMMAND_LONG_RSP_bit)
# define MCI_COMMAND_INTERRUPT				(1 << MCI_COMMAND_INTERRUPT_bit)
# define MCI_COMMAND_PENDING					(1 << MCI_COMMAND_PENDING_bit)
# define MCI_COMMAND_CPSM_ENABLE				(1 << MCI_COMMAND_CPSM_ENABLE_bit)

# define MCI_RESP_CMD_RESP_CMD_bit			0
# define MCI_RESP_CMD_RESP_CMD_mask			0x3F
# define MCI_RESP_CMD_RESP_CMD				(1 << MCI_RESP_CMD_RESP_CMD_bit)

# define MCI_DATA_CTRL_ENABLE_bit			0
# define MCI_DATA_CTRL_DIRECTION_2H_bit	1
# define MCI_DATA_CTRL_STREAM_MODE_bit		2
# define MCI_DATA_CTRL_DMA_EN_bit			3
/* # define MCI_DATA_CTRL_BLOCK_SIZE_bit		4 */
# define MCI_DATA_CTRL_ENABLE					(1 << MCI_DATA_CTRL_ENABLE_bit)
# define MCI_DATA_CTRL_DIRECTION_2H			(1 << MCI_DATA_CTRL_DIRECTION_2H_bit)
# define MCI_DATA_CTRL_STREAM_MODE			(1 << MCI_DATA_CTRL_STREAM_MODE_bit)
# define MCI_DATA_CTRL_DMA_EN					(1 << MCI_DATA_CTRL_DMA_EN_bit)
# define MCI_DATA_CTRL_BLOCK_SIZE_1       0x00
# define MCI_DATA_CTRL_BLOCK_SIZE_2      	0x10
# define MCI_DATA_CTRL_BLOCK_SIZE_4       0x20
# define MCI_DATA_CTRL_BLOCK_SIZE_8       0x30
# define MCI_DATA_CTRL_BLOCK_SIZE_16      0x40
# define MCI_DATA_CTRL_BLOCK_SIZE_32      0x50
# define MCI_DATA_CTRL_BLOCK_SIZE_64      0x60
# define MCI_DATA_CTRL_BLOCK_SIZE_128     0x70
# define MCI_DATA_CTRL_BLOCK_SIZE_256     0x80
# define MCI_DATA_CTRL_BLOCK_SIZE_512     0x90
# define MCI_DATA_CTRL_BLOCK_SIZE_1024    0xA0
# define MCI_DATA_CTRL_BLOCK_SIZE_2048    0xB0

# define MCI_STATUS_CMD_CRC_FAIL_bit			0
# define MCI_STATUS_DATA_CRC_FAIL_bit			1
# define MCI_STATUS_CMD_TIMEOUT_bit				2
# define MCI_STATUS_DATA_TIMEOUT_bit			3
# define MCI_STATUS_TX_UNDERRUN_bit				4
# define MCI_STATUS_RX_OVERRUN_bit				5
# define MCI_STATUS_CMD_RESP_END_bit			6
# define MCI_STATUS_CMD_SENT_bit					7
# define MCI_STATUS_DATA_END_bit					8
# define MCI_STATUS_START_BIT_ERR_bit			9
# define MCI_STATUS_DATA_BLOCK_END_bit			10
# define MCI_STATUS_CMD_ACTIVE_bit				11
# define MCI_STATUS_TX_ACTIVE_bit				12
# define MCI_STATUS_RX_ACTIVE_bit				13
# define MCI_STATUS_TX_FIFO_HALF_EMPTY_bit	14
# define MCI_STATUS_RX_FIFO_HALF_FULL_bit		15
# define MCI_STATUS_TX_FIFO_FULL_bit			16
# define MCI_STATUS_RX_FIFO_FULL_bit			17
# define MCI_STATUS_TX_FIFO_EMPTY_bit			18
# define MCI_STATUS_RX_FIFO_EMPTY_bit			19
# define MCI_STATUS_TX_DATA_AVLBL_bit			20
# define MCI_STATUS_RX_DATA_AVLBL_bit			21
# define MCI_STATUS_CMD_CRC_FAIL				(1 << MCI_STATUS_CMD_CRC_FAIL_bit)
# define MCI_STATUS_DATA_CRC_FAIL			(1 << MCI_STATUS_DATA_CRC_FAIL_bit)
# define MCI_STATUS_CMD_TIMEOUT				(1 << MCI_STATUS_CMD_TIMEOUT_bit)
# define MCI_STATUS_DATA_TIMEOUT				(1 << MCI_STATUS_DATA_TIMEOUT_bit)
# define MCI_STATUS_TX_UNDERRUN				(1 << MCI_STATUS_TX_UNDERRUN_bit)
# define MCI_STATUS_RX_OVERRUN				(1 << MCI_STATUS_RX_OVERRUN_bit)
# define MCI_STATUS_CMD_RESP_END				(1 << MCI_STATUS_CMD_RESP_END_bit)
# define MCI_STATUS_CMD_SENT					(1 << MCI_STATUS_CMD_SENT_bit)
# define MCI_STATUS_DATA_END					(1 << MCI_STATUS_DATA_END_bit)
# define MCI_STATUS_START_BIT_ERR			(1 << MCI_STATUS_START_BIT_ERR_bit)
# define MCI_STATUS_DATA_BLOCK_END			(1 << MCI_STATUS_DATA_BLOCK_END_bit)
# define MCI_STATUS_CMD_ACTIVE				(1 << MCI_STATUS_CMD_ACTIVE_bit)
# define MCI_STATUS_TX_ACTIVE					(1 << MCI_STATUS_TX_ACTIVE_bit)
# define MCI_STATUS_RX_ACTIVE					(1 << MCI_STATUS_RX_ACTIVE_bit)
# define MCI_STATUS_TX_FIFO_HALF_EMPTY		(1 << MCI_STATUS_TX_FIFO_HALF_EMPTY_bit)
# define MCI_STATUS_RX_FIFO_HALF_FULL		(1 << MCI_STATUS_RX_FIFO_HALF_FULL_bit)
# define MCI_STATUS_TX_FIFO_FULL				(1 << MCI_STATUS_TX_FIFO_FULL_bit)
# define MCI_STATUS_RX_FIFO_FULL				(1 << MCI_STATUS_RX_FIFO_FULL_bit)
# define MCI_STATUS_TX_FIFO_EMPTY			(1 << MCI_STATUS_TX_FIFO_EMPTY_bit)
# define MCI_STATUS_RX_FIFO_EMPTY			(1 << MCI_STATUS_RX_FIFO_EMPTY_bit)
# define MCI_STATUS_TX_DATA_AVLBL			(1 << MCI_STATUS_TX_DATA_AVLBL_bit)
# define MCI_STATUS_RX_DATA_AVLBL			(1 << MCI_STATUS_RX_DATA_AVLBL_bit)

# define MCI_CLEAR_CMD_CRC_FAIL_CLR_bit	0
# define MCI_CLEAR_DATA_CRC_FAIL_CLR_bit	1
# define MCI_CLEAR_CMD_TIMEOUT_CLR_bit		2
# define MCI_CLEAR_DATA_TIMEOUT_CLR_bit	3
# define MCI_CLEAR_TX_UNDERRUN_CLR_bit		4
# define MCI_CLEAR_RX_OVERRUN_CLR_bit		5
# define MCI_CLEAR_CMD_RESP_END_CLR_bit	6
# define MCI_CLEAR_CMD_SENT_CLR_bit			7
# define MCI_CLEAR_DATA_END_CLR_bit			8
# define MCI_CLEAR_START_BIT_ERR_CLR_bit	9
# define MCI_CLEAR_DATA_BLOCK_END_CLR_bit	10
# define MCI_CLEAR_CMD_CRC_FAIL_CLR			(1 << MCI_CLEAR_CMD_CRC_FAIL_CLR_bit)
# define MCI_CLEAR_DATA_CRC_FAIL_CLR		(1 << MCI_CLEAR_DATA_CRC_FAIL_CLR_bit)
# define MCI_CLEAR_CMD_TIMEOUT_CLR			(1 << MCI_CLEAR_CMD_TIMEOUT_CLR_bit)
# define MCI_CLEAR_DATA_TIMEOUT_CLR			(1 << MCI_CLEAR_DATA_TIMEOUT_CLR_bit)
# define MCI_CLEAR_TX_UNDERRUN_CLR			(1 << MCI_CLEAR_TX_UNDERRUN_CLR_bit)
# define MCI_CLEAR_RX_OVERRUN_CLR			(1 << MCI_CLEAR_RX_OVERRUN_CLR_bit)
# define MCI_CLEAR_CMD_RESP_END_CLR			(1 << MCI_CLEAR_CMD_RESP_END_CLR_bit)
# define MCI_CLEAR_CMD_SENT_CLR				(1 << MCI_CLEAR_CMD_SENT_CLR_bit)
# define MCI_CLEAR_DATA_END_CLR				(1 << MCI_CLEAR_DATA_END_CLR_bit)
# define MCI_CLEAR_START_BIT_ERR_CLR		(1 << MCI_CLEAR_START_BIT_ERR_CLR_bit)
# define MCI_CLEAR_DATA_BLOCK_END_CLR		(1 << MCI_CLEAR_DATA_BLOCK_END_CLR_bit)

/*------------------------------------------------------------------------------
 System Control Block- SCB modules include Memory Accelerator Module,
 Phase Locked Loop, VPB divider, Power Control, External Interrupt,
 Reset, and Code Security/Debugging
------------------------------------------------------------------------------*/
/*------------------------------------------------------------------------------
 MAM
------------------------------------------------------------------------------*/
#define MEMMAP_MAP_bit					0

#define MEMMAP_MAP_BOOT_value			0
#define MEMMAP_MAP_FLASH_value		1
#define MEMMAP_MAP_RAM_value			2

#define MEMMAP_MAP_BOOT					(MEMMAP_MAP_BOOT_value << MEMMAP_MAP_bit)
#define MEMMAP_MAP_FLASH				(MEMMAP_MAP_FLASH_value << MEMMAP_MAP_bit)
#define MEMMAP_MAP_RAM					(MEMMAP_MAP_RAM_value << MEMMAP_MAP_bit)

/*------------------------------------------------------------------------------
 PLL
------------------------------------------------------------------------------*/
/* PLLCON - PLL Control register */
#define PLLCON_PLLE_bit					0
#define PLLCON_PLLC_bit					1

#define PLLCON_PLLE						(1 << PLLCON_PLLE_bit)
#define PLLCON_PLLC						(1 << PLLCON_PLLC_bit)

/* PLLCFG - PLL Configuration register */
#define PLLCFG_MSEL_bit					0
#define PLLCFG_MSEL0_bit				0
#define PLLCFG_MSEL1_bit				1
#define PLLCFG_MSEL2_bit				2
#define PLLCFG_MSEL3_bit				3
#define PLLCFG_MSEL4_bit				4
#define PLLCFG_PSEL_bit					5
#define PLLCFG_PSEL0_bit				5
#define PLLCFG_PSEL1_bit				6

#define PLLCFG_MSEL0						(1 << PLLCFG_MSEL0_bit)
#define PLLCFG_MSEL1						(1 << PLLCFG_MSEL1_bit)
#define PLLCFG_MSEL2						(1 << PLLCFG_MSEL2_bit)
#define PLLCFG_MSEL3						(1 << PLLCFG_MSEL3_bit)
#define PLLCFG_MSEL4						(1 << PLLCFG_MSEL4_bit)
#define PLLCFG_PSEL0						(1 << PLLCFG_PSEL0_bit)
#define PLLCFG_PSEL1						(1 << PLLCFG_PSEL1_bit)

#define PLLCFG_MSEL_1_value			0
#define PLLCFG_MSEL_2_value			1
#define PLLCFG_MSEL_3_value			2
#define PLLCFG_MSEL_4_value			3
#define PLLCFG_MSEL_5_value			4
#define PLLCFG_MSEL_6_value			5
#define PLLCFG_MSEL_7_value			6
#define PLLCFG_MSEL_8_value			7
#define PLLCFG_MSEL_9_value			8
#define PLLCFG_MSEL_10_value			9
#define PLLCFG_MSEL_11_value			10
#define PLLCFG_MSEL_12_value			11
#define PLLCFG_MSEL_13_value			12
#define PLLCFG_MSEL_14_value			13
#define PLLCFG_MSEL_15_value			14
#define PLLCFG_MSEL_16_value			15
#define PLLCFG_MSEL_17_value			16
#define PLLCFG_MSEL_18_value			17
#define PLLCFG_MSEL_19_value			18
#define PLLCFG_MSEL_20_value			19
#define PLLCFG_MSEL_21_value			20
#define PLLCFG_MSEL_22_value			21
#define PLLCFG_MSEL_23_value			22
#define PLLCFG_MSEL_24_value			23
#define PLLCFG_MSEL_25_value			24
#define PLLCFG_MSEL_26_value			25
#define PLLCFG_MSEL_27_value			26
#define PLLCFG_MSEL_28_value			27
#define PLLCFG_MSEL_29_value			28
#define PLLCFG_MSEL_30_value			29
#define PLLCFG_MSEL_31_value			30
#define PLLCFG_MSEL_32_value			31
#define PLLCFG_MSEL_mask				31

#define PLLCFG_PSEL_1_value			0
#define PLLCFG_PSEL_2_value			1
#define PLLCFG_PSEL_4_value			2
#define PLLCFG_PSEL_8_value			3
#define PLLCFG_PSEL_mask				3

#define PLLCFG_MSEL_1					(PLLCFG_MSEL_1_value << PLLCFG_MSEL_bit)
#define PLLCFG_MSEL_2					(PLLCFG_MSEL_2_value << PLLCFG_MSEL_bit)
#define PLLCFG_MSEL_3					(PLLCFG_MSEL_3_value << PLLCFG_MSEL_bit)
#define PLLCFG_MSEL_4					(PLLCFG_MSEL_4_value << PLLCFG_MSEL_bit)
#define PLLCFG_MSEL_5					(PLLCFG_MSEL_5_value << PLLCFG_MSEL_bit)
#define PLLCFG_MSEL_6					(PLLCFG_MSEL_6_value << PLLCFG_MSEL_bit)
#define PLLCFG_MSEL_7					(PLLCFG_MSEL_7_value << PLLCFG_MSEL_bit)
#define PLLCFG_MSEL_8					(PLLCFG_MSEL_8_value << PLLCFG_MSEL_bit)
#define PLLCFG_MSEL_9					(PLLCFG_MSEL_9_value << PLLCFG_MSEL_bit)
#define PLLCFG_MSEL_10					(PLLCFG_MSEL_10_value << PLLCFG_MSEL_bit)
#define PLLCFG_MSEL_11					(PLLCFG_MSEL_11_value << PLLCFG_MSEL_bit)
#define PLLCFG_MSEL_12					(PLLCFG_MSEL_12_value << PLLCFG_MSEL_bit)
#define PLLCFG_MSEL_13					(PLLCFG_MSEL_13_value << PLLCFG_MSEL_bit)
#define PLLCFG_MSEL_14					(PLLCFG_MSEL_14_value << PLLCFG_MSEL_bit)
#define PLLCFG_MSEL_15					(PLLCFG_MSEL_15_value << PLLCFG_MSEL_bit)
#define PLLCFG_MSEL_16					(PLLCFG_MSEL_16_value << PLLCFG_MSEL_bit)
#define PLLCFG_MSEL_17					(PLLCFG_MSEL_17_value << PLLCFG_MSEL_bit)
#define PLLCFG_MSEL_18					(PLLCFG_MSEL_18_value << PLLCFG_MSEL_bit)
#define PLLCFG_MSEL_19					(PLLCFG_MSEL_19_value << PLLCFG_MSEL_bit)
#define PLLCFG_MSEL_20					(PLLCFG_MSEL_20_value << PLLCFG_MSEL_bit)
#define PLLCFG_MSEL_21					(PLLCFG_MSEL_21_value << PLLCFG_MSEL_bit)
#define PLLCFG_MSEL_22					(PLLCFG_MSEL_22_value << PLLCFG_MSEL_bit)
#define PLLCFG_MSEL_23					(PLLCFG_MSEL_23_value << PLLCFG_MSEL_bit)
#define PLLCFG_MSEL_24					(PLLCFG_MSEL_24_value << PLLCFG_MSEL_bit)
#define PLLCFG_MSEL_25					(PLLCFG_MSEL_25_value << PLLCFG_MSEL_bit)
#define PLLCFG_MSEL_26					(PLLCFG_MSEL_26_value << PLLCFG_MSEL_bit)
#define PLLCFG_MSEL_27					(PLLCFG_MSEL_27_value << PLLCFG_MSEL_bit)
#define PLLCFG_MSEL_28					(PLLCFG_MSEL_28_value << PLLCFG_MSEL_bit)
#define PLLCFG_MSEL_29					(PLLCFG_MSEL_29_value << PLLCFG_MSEL_bit)
#define PLLCFG_MSEL_30					(PLLCFG_MSEL_30_value << PLLCFG_MSEL_bit)
#define PLLCFG_MSEL_31					(PLLCFG_MSEL_31_value << PLLCFG_MSEL_bit)
#define PLLCFG_MSEL_32					(PLLCFG_MSEL_32_value << PLLCFG_MSEL_bit)

#define PLLCFG_PSEL_1					(PLLCFG_PSEL_1_value << PLLCFG_PSEL_bit)
#define PLLCFG_PSEL_2					(PLLCFG_PSEL_2_value << PLLCFG_PSEL_bit)
#define PLLCFG_PSEL_4					(PLLCFG_PSEL_4_value << PLLCFG_PSEL_bit)
#define PLLCFG_PSEL_8					(PLLCFG_PSEL_8_value << PLLCFG_PSEL_bit)

/* PLLSTAT - PLL Status register */
#define PLLSTAT_MSEL_bit					0
#define PLLSTAT_MSEL0_bit					0
#define PLLSTAT_MSEL1_bit					1
#define PLLSTAT_MSEL2_bit					2
#define PLLSTAT_MSEL3_bit					3
#define PLLSTAT_MSEL4_bit					4
#define PLLSTAT_PSEL_bit					5
#define PLLSTAT_PSEL0_bit					5
#define PLLSTAT_PSEL1_bit					6
#define PLLSTAT_PLLE_bit					8
#define PLLSTAT_PLLC_bit					9
#define PLLSTAT_PLOCK_bit					10

#define PLLSTAT_MSEL0						(1 << PLLSTAT_MSEL0_bit)
#define PLLSTAT_MSEL1						(1 << PLLSTAT_MSEL1_bit)
#define PLLSTAT_MSEL2						(1 << PLLSTAT_MSEL2_bit)
#define PLLSTAT_MSEL3						(1 << PLLSTAT_MSEL3_bit)
#define PLLSTAT_MSEL4						(1 << PLLSTAT_MSEL4_bit)
#define PLLSTAT_PSEL0						(1 << PLLSTAT_PSEL0_bit)
#define PLLSTAT_PSEL1						(1 << PLLSTAT_PSEL1_bit)
#define PLLSTAT_PLLE							(1 << PLLSTAT_PLLE_bit)
#define PLLSTAT_PLLC							(1 << PLLSTAT_PLLC_bit)
#define PLLSTAT_PLOCK						(1 << PLLSTAT_PLOCK_bit)

#define PLLSTAT_MSEL_1_value				0
#define PLLSTAT_MSEL_2_value				1
#define PLLSTAT_MSEL_3_value				2
#define PLLSTAT_MSEL_4_value				3
#define PLLSTAT_MSEL_5_value				4
#define PLLSTAT_MSEL_6_value				5
#define PLLSTAT_MSEL_7_value				6
#define PLLSTAT_MSEL_8_value				7
#define PLLSTAT_MSEL_9_value				8
#define PLLSTAT_MSEL_10_value				9
#define PLLSTAT_MSEL_11_value				10
#define PLLSTAT_MSEL_12_value				11
#define PLLSTAT_MSEL_13_value				12
#define PLLSTAT_MSEL_14_value				13
#define PLLSTAT_MSEL_15_value				14
#define PLLSTAT_MSEL_16_value				15
#define PLLSTAT_MSEL_17_value				16
#define PLLSTAT_MSEL_18_value				17
#define PLLSTAT_MSEL_19_value				18
#define PLLSTAT_MSEL_20_value				19
#define PLLSTAT_MSEL_21_value				20
#define PLLSTAT_MSEL_22_value				21
#define PLLSTAT_MSEL_23_value				22
#define PLLSTAT_MSEL_24_value				23
#define PLLSTAT_MSEL_25_value				24
#define PLLSTAT_MSEL_26_value				25
#define PLLSTAT_MSEL_27_value				26
#define PLLSTAT_MSEL_28_value				27
#define PLLSTAT_MSEL_29_value				28
#define PLLSTAT_MSEL_30_value				29
#define PLLSTAT_MSEL_31_value				30
#define PLLSTAT_MSEL_32_value				31
#define PLLSTAT_MSEL_mask					31

#define PLLSTAT_PSEL_1_value				0
#define PLLSTAT_PSEL_2_value				1
#define PLLSTAT_PSEL_4_value				2
#define PLLSTAT_PSEL_8_value				3
#define PLLSTAT_PSEL_mask					3

#define PLLSTAT_MSEL_1						(PLLSTAT_MSEL_1_value << PLLSTAT_MSEL_bit)
#define PLLSTAT_MSEL_2						(PLLSTAT_MSEL_2_value << PLLSTAT_MSEL_bit)
#define PLLSTAT_MSEL_3						(PLLSTAT_MSEL_3_value << PLLSTAT_MSEL_bit)
#define PLLSTAT_MSEL_4						(PLLSTAT_MSEL_4_value << PLLSTAT_MSEL_bit)
#define PLLSTAT_MSEL_5						(PLLSTAT_MSEL_5_value << PLLSTAT_MSEL_bit)
#define PLLSTAT_MSEL_6						(PLLSTAT_MSEL_6_value << PLLSTAT_MSEL_bit)
#define PLLSTAT_MSEL_7						(PLLSTAT_MSEL_7_value << PLLSTAT_MSEL_bit)
#define PLLSTAT_MSEL_8						(PLLSTAT_MSEL_8_value << PLLSTAT_MSEL_bit)
#define PLLSTAT_MSEL_9						(PLLSTAT_MSEL_9_value << PLLSTAT_MSEL_bit)
#define PLLSTAT_MSEL_10						(PLLSTAT_MSEL_10_value << PLLSTAT_MSEL_bit)
#define PLLSTAT_MSEL_11						(PLLSTAT_MSEL_11_value << PLLSTAT_MSEL_bit)
#define PLLSTAT_MSEL_12						(PLLSTAT_MSEL_12_value << PLLSTAT_MSEL_bit)
#define PLLSTAT_MSEL_13						(PLLSTAT_MSEL_13_value << PLLSTAT_MSEL_bit)
#define PLLSTAT_MSEL_14						(PLLSTAT_MSEL_14_value << PLLSTAT_MSEL_bit)
#define PLLSTAT_MSEL_15						(PLLSTAT_MSEL_15_value << PLLSTAT_MSEL_bit)
#define PLLSTAT_MSEL_16						(PLLSTAT_MSEL_16_value << PLLSTAT_MSEL_bit)
#define PLLSTAT_MSEL_17						(PLLSTAT_MSEL_17_value << PLLSTAT_MSEL_bit)
#define PLLSTAT_MSEL_18						(PLLSTAT_MSEL_18_value << PLLSTAT_MSEL_bit)
#define PLLSTAT_MSEL_19						(PLLSTAT_MSEL_19_value << PLLSTAT_MSEL_bit)
#define PLLSTAT_MSEL_20						(PLLSTAT_MSEL_20_value << PLLSTAT_MSEL_bit)
#define PLLSTAT_MSEL_21						(PLLSTAT_MSEL_21_value << PLLSTAT_MSEL_bit)
#define PLLSTAT_MSEL_22						(PLLSTAT_MSEL_22_value << PLLSTAT_MSEL_bit)
#define PLLSTAT_MSEL_23						(PLLSTAT_MSEL_23_value << PLLSTAT_MSEL_bit)
#define PLLSTAT_MSEL_24						(PLLSTAT_MSEL_24_value << PLLSTAT_MSEL_bit)
#define PLLSTAT_MSEL_25						(PLLSTAT_MSEL_25_value << PLLSTAT_MSEL_bit)
#define PLLSTAT_MSEL_26						(PLLSTAT_MSEL_26_value << PLLSTAT_MSEL_bit)
#define PLLSTAT_MSEL_27						(PLLSTAT_MSEL_27_value << PLLSTAT_MSEL_bit)
#define PLLSTAT_MSEL_28						(PLLSTAT_MSEL_28_value << PLLSTAT_MSEL_bit)
#define PLLSTAT_MSEL_29						(PLLSTAT_MSEL_29_value << PLLSTAT_MSEL_bit)
#define PLLSTAT_MSEL_30						(PLLSTAT_MSEL_30_value << PLLSTAT_MSEL_bit)
#define PLLSTAT_MSEL_31						(PLLSTAT_MSEL_31_value << PLLSTAT_MSEL_bit)
#define PLLSTAT_MSEL_32						(PLLSTAT_MSEL_32_value << PLLSTAT_MSEL_bit)

#define PLLSTAT_PSEL_1						(PLLSTAT_PSEL_1_value << PLLSTAT_PSEL_bit)
#define PLLSTAT_PSEL_2						(PLLSTAT_PSEL_2_value << PLLSTAT_PSEL_bit)
#define PLLSTAT_PSEL_4						(PLLSTAT_PSEL_4_value << PLLSTAT_PSEL_bit)
#define PLLSTAT_PSEL_8						(PLLSTAT_PSEL_8_value << PLLSTAT_PSEL_bit)

/* PLLFEED - PLL Feed register */
#define PLLFEED_FIRST						0xAA
#define PLLFEED_SECOND						0x55

/*------------------------------------------------------------------------------
 Power Control
------------------------------------------------------------------------------*/
#define PCON_IDL_bit							0
#define PCON_PD_bit							1

#define PCON_IDL								(1 << PCON_IDL_bit)
#define PCON_PD								(1 << PCON_PD_bit)

/* PCONP - Power Control for Peripherals register */
# define PCONP_PCTIM0_bit					1
# define PCONP_PCTIM1_bit					2
# define PCONP_PCUART0_bit					3
# define PCONP_PCUART1_bit					4
# define PCONP_PCPWM0_bit					5
# define PCONP_PCPWM1_bit					6
# define PCONP_PCI2C0_bit					7
# define PCONP_PCSPI_bit					8
# define PCONP_PCRTC_bit					9
# define PCONP_PCSSP1_bit					10
# define PCONP_PCEMC_bit					11
# define PCONP_PCAD_bit						12
# define PCONP_PCAN1_bit					13
# define PCONP_PCAN2_bit					14
/* reserved 15-18 */
# define PCONP_PCI2C1_bit					19
# define PCONP_PCLCD_bit					20
# define PCONP_PCSSP0_bit					21
# define PCONP_PCTIM2_bit					22
# define PCONP_PCTIM3_bit					23
# define PCONP_PCUART2_bit					24
# define PCONP_PCUART3_bit					25
# define PCONP_PCI2C2_bit					26
# define PCONP_PCI2S_bit					27
# define PCONP_PCSDC_bit					28
# define PCONP_PCGPDMA_bit					29
# define PCONP_PCENET_bit					30
# define PCONP_PCUSB_bit					31

# define PCONP_PCTIM0						(1 << PCONP_PCTIM0_bit)
# define PCONP_PCTIM1						(1 << PCONP_PCTIM1_bit)
# define PCONP_PCUART0						(1 << PCONP_PCUART0_bit)
# define PCONP_PCUART1						(1 << PCONP_PCUART1_bit)
# define PCONP_PCPWM0						(1 << PCONP_PCPWM0_bit)
# define PCONP_PCPWM1						(1 << PCONP_PCPWM1_bit)
# define PCONP_PCI2C0						(1 << PCONP_PCI2C0_bit)
# define PCONP_PCSPI							(1 << PCONP_PCSPI_bit)
# define PCONP_PCRTC							(1 << PCONP_PCRTC_bit)
# define PCONP_PCSSP1						(1 << PCONP_PCSSP1_bit)
# define PCONP_PCEMC							(1 << PCONP_PCEMC_bit)
# define PCONP_PCAD							(1 << PCONP_PCAD_bit)
# define PCONP_PCAN1							(1 << PCONP_PCAN1_bit)
# define PCONP_PCAN2							(1 << PCONP_PCAN2_bit)
# define PCONP_PCI2C1						(1 << PCONP_PCI2C1_bit)
# define PCONP_PCLCD							(1 << PCONP_PCLCD_bit)
# define PCONP_PCSSP0						(1 << PCONP_PCSSP0_bit)
# define PCONP_PCTIM2						(1 << PCONP_PCTIM2_bit)
# define PCONP_PCTIM3						(1 << PCONP_PCTIM3_bit)
# define PCONP_PCUART2						(1 << PCONP_PCUART2_bit)
# define PCONP_PCUART3						(1 << PCONP_PCUART3_bit)
# define PCONP_PCI2C2						(1 << PCONP_PCI2C2_bit)
# define PCONP_PCI2S							(1 << PCONP_PCI2S_bit)
# define PCONP_PCSDC							(1 << PCONP_PCSDC_bit)
# define PCONP_PCGPDMA						(1 << PCONP_PCGPDMA_bit)
# define PCONP_PCENET						(1 << PCONP_PCENET_bit)
# define PCONP_PCUSB							(1 << PCONP_PCUSB_bit)

/*------------------------------------------------------------------------------
 APBDIV - APB Divider register. NOTE: LPC24XX has CLKSRCSEL instead.
------------------------------------------------------------------------------*/
# define CLKSRC 0x01 /* 0x01 selects the main oscillator as PLL clock source */

#define APBDIV_APBDIV_bit					0
#define APBDIV_APBDIV0_bit					0
#define APBDIV_APBDIV1_bit					1

#define APBDIV_APBDIV						(1 << APBDIV_APBDIV_bit)
#define APBDIV_APBDIV0						(1 << APBDIV_APBDIV0_bit)
#define APBDIV_APBDIV1						(1 << APBDIV_APBDIV1_bit)

#define APBDIV_APBDIV_4_value				0
#define APBDIV_APBDIV_1_value				1
#define APBDIV_APBDIV_2_value				2
#define APBDIV_APBDIV_mask					3

#define APBDIV_APBDIV_4						(APBDIV_APBDIV_4_value << APBDIV_APBDIV_bit)
#define APBDIV_APBDIV_1						(APBDIV_APBDIV_1_value << APBDIV_APBDIV_bit)
#define APBDIV_APBDIV_2						(APBDIV_APBDIV_2_value << APBDIV_APBDIV_bit)

/*------------------------------------------------------------------------------
 PCLKSEL0
------------------------------------------------------------------------------*/
# define PCLK_FREQ_DIV1_value             1
# define PCLK_FREQ_DIV2_value             2
# define PCLK_FREQ_DIV4_value             0
# define PCLK_FREQ_DIV8_value             3

# define PCLKSEL0_WTD_bit                 0
# define PCLKSEL0_TIMER0_bit              2
# define PCLKSEL0_TIMER1_bit              4
# define PCLKSEL0_UART0_bit               6
# define PCLKSEL0_UART1_bit               8
# define PCLKSEL0_PWM0_bit                10
# define PCLKSEL0_PWM1_bit                12
# define PCLKSEL0_I2C0_bit                14
# define PCLKSEL0_SPI_bit                 16
# define PCLKSEL0_RTC_bit                 18
# define PCLKSEL0_SSP1_bit                20
# define PCLKSEL0_DAC_bit                 22
# define PCLKSEL0_ADC_bit                 24
# define PCLKSEL0_CAN1_bit                26
# define PCLKSEL0_CAN2_bit                28
# define PCLKSEL0_ACF_bit                 30

# define PCLKSEL0_WTD_FREQ_DIV1           (PCLK_FREQ_DIV1_value << PCLKSEL0_WTD_bit)
# define PCLKSEL0_WTD_FREQ_DIV2           (PCLK_FREQ_DIV2_value << PCLKSEL0_WTD_bit)
# define PCLKSEL0_WTD_FREQ_DIV4           (PCLK_FREQ_DIV4_value << PCLKSEL0_WTD_bit)
# define PCLKSEL0_WTD_FREQ_DIV8           (PCLK_FREQ_DIV8_value << PCLKSEL0_WTD_bit)

# define PCLKSEL0_TIMER0_FREQ_DIV1        (PCLK_FREQ_DIV1_value << PCLKSEL0_TIMER0_bit)
# define PCLKSEL0_TIMER0_FREQ_DIV2        (PCLK_FREQ_DIV2_value << PCLKSEL0_TIMER0_bit)
# define PCLKSEL0_TIMER0_FREQ_DIV4        (PCLK_FREQ_DIV4_value << PCLKSEL0_TIMER0_bit)
# define PCLKSEL0_TIMER0_FREQ_DIV8        (PCLK_FREQ_DIV8_value << PCLKSEL0_TIMER0_bit)

# define PCLKSEL0_TIMER1_FREQ_DIV1        (PCLK_FREQ_DIV1_value << PCLKSEL0_TIMER1_bit)
# define PCLKSEL0_TIMER1_FREQ_DIV2        (PCLK_FREQ_DIV2_value << PCLKSEL0_TIMER1_bit)
# define PCLKSEL0_TIMER1_FREQ_DIV4        (PCLK_FREQ_DIV4_value << PCLKSEL0_TIMER1_bit)
# define PCLKSEL0_TIMER1_FREQ_DIV8        (PCLK_FREQ_DIV8_value << PCLKSEL0_TIMER1_bit)

# define PCLKSEL0_UART0_FREQ_DIV1        (PCLK_FREQ_DIV1_value << PCLKSEL0_UART0_bit)
# define PCLKSEL0_UART0_FREQ_DIV2        (PCLK_FREQ_DIV2_value << PCLKSEL0_UART0_bit)
# define PCLKSEL0_UART0_FREQ_DIV4        (PCLK_FREQ_DIV4_value << PCLKSEL0_UART0_bit)
# define PCLKSEL0_UART0_FREQ_DIV8        (PCLK_FREQ_DIV8_value << PCLKSEL0_UART0_bit)

# define PCLKSEL0_UART1_FREQ_DIV1        (PCLK_FREQ_DIV1_value << PCLKSEL0_UART1_bit)
# define PCLKSEL0_UART1_FREQ_DIV2        (PCLK_FREQ_DIV2_value << PCLKSEL0_UART1_bit)
# define PCLKSEL0_UART1_FREQ_DIV4        (PCLK_FREQ_DIV4_value << PCLKSEL0_UART1_bit)
# define PCLKSEL0_UART1_FREQ_DIV8        (PCLK_FREQ_DIV8_value << PCLKSEL0_UART1_bit)

# define PCLKSEL0_PWM0_FREQ_DIV1        (PCLK_FREQ_DIV1_value << PCLKSEL0_PWM0_bit)
# define PCLKSEL0_PWM0_FREQ_DIV2        (PCLK_FREQ_DIV2_value << PCLKSEL0_PWM0_bit)
# define PCLKSEL0_PWM0_FREQ_DIV4        (PCLK_FREQ_DIV4_value << PCLKSEL0_PWM0_bit)
# define PCLKSEL0_PWM0_FREQ_DIV8        (PCLK_FREQ_DIV8_value << PCLKSEL0_PWM0_bit)

# define PCLKSEL0_PWM1_FREQ_DIV1        (PCLK_FREQ_DIV1_value << PCLKSEL0_PWM1_bit)
# define PCLKSEL0_PWM1_FREQ_DIV2        (PCLK_FREQ_DIV2_value << PCLKSEL0_PWM1_bit)
# define PCLKSEL0_PWM1_FREQ_DIV4        (PCLK_FREQ_DIV4_value << PCLKSEL0_PWM1_bit)
# define PCLKSEL0_PWM1_FREQ_DIV8        (PCLK_FREQ_DIV8_value << PCLKSEL0_PWM1_bit)

# define PCLKSEL0_I2C0_FREQ_DIV1        (PCLK_FREQ_DIV1_value << PCLKSEL0_I2C0_bit)
# define PCLKSEL0_I2C0_FREQ_DIV2        (PCLK_FREQ_DIV2_value << PCLKSEL0_I2C0_bit)
# define PCLKSEL0_I2C0_FREQ_DIV4        (PCLK_FREQ_DIV4_value << PCLKSEL0_I2C0_bit)
# define PCLKSEL0_I2C0_FREQ_DIV8        (PCLK_FREQ_DIV8_value << PCLKSEL0_I2C0_bit)

# define PCLKSEL0_SPI_FREQ_DIV1        (PCLK_FREQ_DIV1_value << PCLKSEL0_SPI_bit)
# define PCLKSEL0_SPI_FREQ_DIV2        (PCLK_FREQ_DIV2_value << PCLKSEL0_SPI_bit)
# define PCLKSEL0_SPI_FREQ_DIV4        (PCLK_FREQ_DIV4_value << PCLKSEL0_SPI_bit)
# define PCLKSEL0_SPI_FREQ_DIV8        (PCLK_FREQ_DIV8_value << PCLKSEL0_SPI_bit)

# define PCLKSEL0_RTC_FREQ_DIV1        (PCLK_FREQ_DIV1_value << PCLKSEL0_RTC_bit)
# define PCLKSEL0_RTC_FREQ_DIV2        (PCLK_FREQ_DIV2_value << PCLKSEL0_RTC_bit)
# define PCLKSEL0_RTC_FREQ_DIV4        (PCLK_FREQ_DIV4_value << PCLKSEL0_RTC_bit)
# define PCLKSEL0_RTC_FREQ_DIV8        (PCLK_FREQ_DIV8_value << PCLKSEL0_RTC_bit)

# define PCLKSEL0_SSP1_FREQ_DIV1       (PCLK_FREQ_DIV1_value << PCLKSEL0_SSP1_bit)
# define PCLKSEL0_SSP1_FREQ_DIV2       (PCLK_FREQ_DIV2_value << PCLKSEL0_SSP1_bit)
# define PCLKSEL0_SSP1_FREQ_DIV4       (PCLK_FREQ_DIV4_value << PCLKSEL0_SSP1_bit)
# define PCLKSEL0_SSP1_FREQ_DIV8       (PCLK_FREQ_DIV8_value << PCLKSEL0_SSP1_bit)

# define PCLKSEL0_DAC_FREQ_DIV1       (PCLK_FREQ_DIV1_value << PCLKSEL0_DAC_bit)
# define PCLKSEL0_DAC_FREQ_DIV2       (PCLK_FREQ_DIV2_value << PCLKSEL0_DAC_bit)
# define PCLKSEL0_DAC_FREQ_DIV4       (PCLK_FREQ_DIV4_value << PCLKSEL0_DAC_bit)
# define PCLKSEL0_DAC_FREQ_DIV8       (PCLK_FREQ_DIV8_value << PCLKSEL0_DAC_bit)

# define PCLKSEL0_ADC_FREQ_DIV1       (PCLK_FREQ_DIV1_value << PCLKSEL0_ADC_bit)
# define PCLKSEL0_ADC_FREQ_DIV2       (PCLK_FREQ_DIV2_value << PCLKSEL0_ADC_bit)
# define PCLKSEL0_ADC_FREQ_DIV4       (PCLK_FREQ_DIV4_value << PCLKSEL0_ADC_bit)
# define PCLKSEL0_ADC_FREQ_DIV8       (PCLK_FREQ_DIV8_value << PCLKSEL0_ADC_bit)

# define PCLKSEL0_CAN1_FREQ_DIV1       (PCLK_FREQ_DIV1_value << PCLKSEL0_CAN1_bit)
# define PCLKSEL0_CAN1_FREQ_DIV2       (PCLK_FREQ_DIV2_value << PCLKSEL0_CAN1_bit)
# define PCLKSEL0_CAN1_FREQ_DIV4       (PCLK_FREQ_DIV4_value << PCLKSEL0_CAN1_bit)
# define PCLKSEL0_CAN1_FREQ_DIV8       (PCLK_FREQ_DIV8_value << PCLKSEL0_CAN1_bit)

# define PCLKSEL0_CAN2_FREQ_DIV1       (PCLK_FREQ_DIV1_value << PCLKSEL0_CAN2_bit)
# define PCLKSEL0_CAN2_FREQ_DIV2       (PCLK_FREQ_DIV2_value << PCLKSEL0_CAN2_bit)
# define PCLKSEL0_CAN2_FREQ_DIV4       (PCLK_FREQ_DIV4_value << PCLKSEL0_CAN2_bit)
# define PCLKSEL0_CAN2_FREQ_DIV8       (PCLK_FREQ_DIV8_value << PCLKSEL0_CAN2_bit)

# define PCLKSEL0_ACF_FREQ_DIV1       (PCLK_FREQ_DIV1_value << PCLKSEL0_ACF_bit)
# define PCLKSEL0_ACF_FREQ_DIV2       (PCLK_FREQ_DIV2_value << PCLKSEL0_ACF_bit)
# define PCLKSEL0_ACF_FREQ_DIV4       (PCLK_FREQ_DIV4_value << PCLKSEL0_ACF_bit)
# define PCLKSEL0_ACF_FREQ_DIV8       (PCLK_FREQ_DIV8_value << PCLKSEL0_ACF_bit)

/*------------------------------------------------------------------------------
 PCLKSEL1
------------------------------------------------------------------------------*/
# define PCLKSEL1_BAT_RAM_bit          0
# define PCLKSEL1_GPIO_bit             2
# define PCLKSEL1_PCB_bit              4
# define PCLKSEL1_I2C1_bit             6
# define PCLKSEL1_SSP0_bit             10
# define PCLKSEL1_TIMER2_bit           12
# define PCLKSEL1_TIMER3_bit           14
# define PCLKSEL1_UART2_bit            16
# define PCLKSEL1_UART3_bit            18
# define PCLKSEL1_I2C2_bit             20
# define PCLKSEL1_I2S_bit              22
# define PCLKSEL1_MCI_bit              24
# define PCLKSEL1_SYSCON_bit           28

# define PCLKSEL1_BAT_RAM_FREQ_DIV1    (PCLK_FREQ_DIV1_value << PCLKSEL1_BAT_RAM_bit)
# define PCLKSEL1_BAT_RAM_FREQ_DIV2    (PCLK_FREQ_DIV2_value << PCLKSEL1_BAT_RAM_bit)
# define PCLKSEL1_BAT_RAM_FREQ_DIV4    (PCLK_FREQ_DIV4_value << PCLKSEL1_BAT_RAM_bit)
# define PCLKSEL1_BAT_RAM_FREQ_DIV8    (PCLK_FREQ_DIV8_value << PCLKSEL1_BAT_RAM_bit)

# define PCLKSEL1_GPIO_FREQ_DIV1       (PCLK_FREQ_DIV1_value << PCLKSEL1_GPIO_bit)
# define PCLKSEL1_GPIO_FREQ_DIV2       (PCLK_FREQ_DIV2_value << PCLKSEL1_GPIO_bit)
# define PCLKSEL1_GPIO_FREQ_DIV4       (PCLK_FREQ_DIV4_value << PCLKSEL1_GPIO_bit)
# define PCLKSEL1_GPIO_FREQ_DIV8       (PCLK_FREQ_DIV8_value << PCLKSEL1_GPIO_bit)

# define PCLKSEL1_PCB_FREQ_DIV1        (PCLK_FREQ_DIV1_value << PCLKSEL1_PCB_bit)
# define PCLKSEL1_PCB_FREQ_DIV2        (PCLK_FREQ_DIV2_value << PCLKSEL1_PCB_bit)
# define PCLKSEL1_PCB_FREQ_DIV4        (PCLK_FREQ_DIV4_value << PCLKSEL1_PCB_bit)
# define PCLKSEL1_PCB_FREQ_DIV8        (PCLK_FREQ_DIV8_value << PCLKSEL1_PCB_bit)

# define PCLKSEL1_I2C1_FREQ_DIV1       (PCLK_FREQ_DIV1_value << PCLKSEL1_I2C1_bit)
# define PCLKSEL1_I2C1_FREQ_DIV2       (PCLK_FREQ_DIV2_value << PCLKSEL1_I2C1_bit)
# define PCLKSEL1_I2C1_FREQ_DIV4       (PCLK_FREQ_DIV4_value << PCLKSEL1_I2C1_bit)
# define PCLKSEL1_I2C1_FREQ_DIV8       (PCLK_FREQ_DIV8_value << PCLKSEL1_I2C1_bit)

# define PCLKSEL1_SSP0_FREQ_DIV1       (PCLK_FREQ_DIV1_value << PCLKSEL1_SSP0_bit)
# define PCLKSEL1_SSP0_FREQ_DIV2       (PCLK_FREQ_DIV2_value << PCLKSEL1_SSP0_bit)
# define PCLKSEL1_SSP0_FREQ_DIV4       (PCLK_FREQ_DIV4_value << PCLKSEL1_SSP0_bit)
# define PCLKSEL1_SSP0_FREQ_DIV8       (PCLK_FREQ_DIV8_value << PCLKSEL1_SSP0_bit)

# define PCLKSEL1_TIMER2_FREQ_DIV1     (PCLK_FREQ_DIV1_value << PCLKSEL1_TIMER2_bit)
# define PCLKSEL1_TIMER2_FREQ_DIV2     (PCLK_FREQ_DIV2_value << PCLKSEL1_TIMER2_bit)
# define PCLKSEL1_TIMER2_FREQ_DIV4     (PCLK_FREQ_DIV4_value << PCLKSEL1_TIMER2_bit)
# define PCLKSEL1_TIMER2_FREQ_DIV8     (PCLK_FREQ_DIV8_value << PCLKSEL1_TIMER2_bit)

# define PCLKSEL1_TIMER3_FREQ_DIV1     (PCLK_FREQ_DIV1_value << PCLKSEL1_TIMER3_bit)
# define PCLKSEL1_TIMER3_FREQ_DIV2     (PCLK_FREQ_DIV2_value << PCLKSEL1_TIMER3_bit)
# define PCLKSEL1_TIMER3_FREQ_DIV4     (PCLK_FREQ_DIV4_value << PCLKSEL1_TIMER3_bit)
# define PCLKSEL1_TIMER3_FREQ_DIV8     (PCLK_FREQ_DIV8_value << PCLKSEL1_TIMER3_bit)

# define PCLKSEL1_UART2_FREQ_DIV1     (PCLK_FREQ_DIV1_value << PCLKSEL1_UART2_bit)
# define PCLKSEL1_UART2_FREQ_DIV2     (PCLK_FREQ_DIV2_value << PCLKSEL1_UART2_bit)
# define PCLKSEL1_UART2_FREQ_DIV4     (PCLK_FREQ_DIV4_value << PCLKSEL1_UART2_bit)
# define PCLKSEL1_UART2_FREQ_DIV8     (PCLK_FREQ_DIV8_value << PCLKSEL1_UART2_bit)

# define PCLKSEL1_UART3_FREQ_DIV1     (PCLK_FREQ_DIV1_value << PCLKSEL1_UART3_bit)
# define PCLKSEL1_UART3_FREQ_DIV2     (PCLK_FREQ_DIV2_value << PCLKSEL1_UART3_bit)
# define PCLKSEL1_UART3_FREQ_DIV4     (PCLK_FREQ_DIV4_value << PCLKSEL1_UART3_bit)
# define PCLKSEL1_UART3_FREQ_DIV8     (PCLK_FREQ_DIV8_value << PCLKSEL1_UART3_bit)

# define PCLKSEL1_I2C2_FREQ_DIV1       (PCLK_FREQ_DIV1_value << PCLKSEL1_I2C2_bit)
# define PCLKSEL1_I2C2_FREQ_DIV2       (PCLK_FREQ_DIV2_value << PCLKSEL1_I2C2_bit)
# define PCLKSEL1_I2C2_FREQ_DIV4       (PCLK_FREQ_DIV4_value << PCLKSEL1_I2C2_bit)
# define PCLKSEL1_I2C2_FREQ_DIV8       (PCLK_FREQ_DIV8_value << PCLKSEL1_I2C2_bit)

# define PCLKSEL1_I2S_FREQ_DIV1       (PCLK_FREQ_DIV1_value << PCLKSEL1_I2S_bit)
# define PCLKSEL1_I2S_FREQ_DIV2       (PCLK_FREQ_DIV2_value << PCLKSEL1_I2S_bit)
# define PCLKSEL1_I2S_FREQ_DIV4       (PCLK_FREQ_DIV4_value << PCLKSEL1_I2S_bit)
# define PCLKSEL1_I2S_FREQ_DIV8       (PCLK_FREQ_DIV8_value << PCLKSEL1_I2S_bit)

# define PCLKSEL1_MCI_FREQ_DIV1       (PCLK_FREQ_DIV1_value << PCLKSEL1_MCI_bit)
# define PCLKSEL1_MCI_FREQ_DIV2       (PCLK_FREQ_DIV2_value << PCLKSEL1_MCI_bit)
# define PCLKSEL1_MCI_FREQ_DIV4       (PCLK_FREQ_DIV4_value << PCLKSEL1_MCI_bit)
# define PCLKSEL1_MCI_FREQ_DIV8       (PCLK_FREQ_DIV8_value << PCLKSEL1_MCI_bit)

# define PCLKSEL1_SYSCON_FREQ_DIV1     (PCLK_FREQ_DIV1_value << PCLKSEL1_SYSCON_bit)
# define PCLKSEL1_SYSCON_FREQ_DIV2     (PCLK_FREQ_DIV2_value << PCLKSEL1_SYSCON_bit)
# define PCLKSEL1_SYSCON_FREQ_DIV4     (PCLK_FREQ_DIV4_value << PCLKSEL1_SYSCON_bit)
# define PCLKSEL1_SYSCON_FREQ_DIV8     (PCLK_FREQ_DIV8_value << PCLKSEL1_SYSCON_bit)
/*------------------------------------------------------------------------------
 External Interrupts
------------------------------------------------------------------------------*/
# define EXTINT_EINT0_bit					0
# define EXTINT_EINT1_bit					1
# define EXTINT_EINT2_bit					2
# define EXTINT_EINT3_bit					3

# define EXTINT_EINT0						(1 << EXTINT_EINT0_bit)
# define EXTINT_EINT1						(1 << EXTINT_EINT1_bit)
# define EXTINT_EINT2						(1 << EXTINT_EINT2_bit)
# define EXTINT_EINT3						(1 << EXTINT_EINT3_bit)

/*------------------------------------------------------------------------------
 INTWAKE - Interrupt Wake-up register
------------------------------------------------------------------------------*/
#define INTWAKE_EXTWAKE0_bit				0
#define INTWAKE_EXTWAKE1_bit				1
#define INTWAKE_EXTWAKE2_bit				2
#define INTWAKE_RTCWAKE_bit				15

#define INTWAKE_EXTWAKE0					(1 << INTWAKE_EXTWAKE0_bit)
#define INTWAKE_EXTWAKE1					(1 << INTWAKE_EXTWAKE1_bit)
#define INTWAKE_EXTWAKE2					(1 << INTWAKE_EXTWAKE2_bit)
#define INTWAKE_RTCWAKE						(1 << INTWAKE_RTCWAKE_bit)

/*------------------------------------------------------------------------------
 EXTMODE - External Interrupt Mode register
------------------------------------------------------------------------------*/
# define EXTMODE_EXTMODE0_bit					0
# define EXTMODE_EXTMODE1_bit					1
# define EXTMODE_EXTMODE2_bit					2
# define EXTMODE_EXTMODE3_bit					2

# define EXTMODE_EXTMODE0_LEVEL_value		0
# define EXTMODE_EXTMODE0_EDGE_value		1
# define EXTMODE_EXTMODE1_LEVEL_value		0
# define EXTMODE_EXTMODE1_EDGE_value		1
# define EXTMODE_EXTMODE2_LEVEL_value		0
# define EXTMODE_EXTMODE2_EDGE_value		1
# define EXTMODE_EXTMODE3_LEVEL_value		0
# define EXTMODE_EXTMODE3_EDGE_value		1

# define EXTMODE_EXTMODE0_LEVEL				(EXTMODE_EXTMODE0_LEVEL_value << EXTMODE_EXTMODE0_bit)
# define EXTMODE_EXTMODE0_EDGE				(EXTMODE_EXTMODE0_EDGE_value << EXTMODE_EXTMODE0_bit)
# define EXTMODE_EXTMODE1_LEVEL				(EXTMODE_EXTMODE1_LEVEL_value << EXTMODE_EXTMODE1_bit)
# define EXTMODE_EXTMODE1_EDGE				(EXTMODE_EXTMODE1_EDGE_value << EXTMODE_EXTMODE1_bit)
# define EXTMODE_EXTMODE2_LEVEL				(EXTMODE_EXTMODE2_LEVEL_value << EXTMODE_EXTMODE2_bit)
# define EXTMODE_EXTMODE2_EDGE				(EXTMODE_EXTMODE2_EDGE_value << EXTMODE_EXTMODE2_bit)
# define EXTMODE_EXTMODE3_LEVEL				(EXTMODE_EXTMODE3_LEVEL_value << EXTMODE_EXTMODE3_bit)
# define EXTMODE_EXTMODE3_EDGE				(EXTMODE_EXTMODE3_EDGE_value << EXTMODE_EXTMODE3_bit)

/*------------------------------------------------------------------------------
 EXTPOLAR - External Interrupt Polarity register
------------------------------------------------------------------------------*/
# define EXTPOLAR_EXTPOLAR0_bit				0
# define EXTPOLAR_EXTPOLAR1_bit				1
# define EXTPOLAR_EXTPOLAR2_bit				2
# define EXTPOLAR_EXTPOLAR3_bit				3

# define EXTPOLAR_EXTPOLAR0_FALLING_value	0
# define EXTPOLAR_EXTPOLAR0_RISING_value	1
# define EXTPOLAR_EXTPOLAR1_FALLING_value	0
# define EXTPOLAR_EXTPOLAR1_RISING_value	1
# define EXTPOLAR_EXTPOLAR2_FALLING_value	0
# define EXTPOLAR_EXTPOLAR2_RISING_value	1
# define EXTPOLAR_EXTPOLAR3_FALLING_value	0
# define EXTPOLAR_EXTPOLAR3_RISING_value	1

# define EXTPOLAR_EXTPOLAR0_FALLING			(EXTPOLAR_EXTPOLAR0_FALLING_value << EXTPOLAR_EXTPOLAR0_bit)
# define EXTPOLAR_EXTPOLAR0_RISING			(EXTPOLAR_EXTPOLAR0_RISING_value << EXTPOLAR_EXTPOLAR0_bit)
# define EXTPOLAR_EXTPOLAR1_FALLING			(EXTPOLAR_EXTPOLAR1_FALLING_value << EXTPOLAR_EXTPOLAR1_bit)
# define EXTPOLAR_EXTPOLAR1_RISING			(EXTPOLAR_EXTPOLAR1_RISING_value << EXTPOLAR_EXTPOLAR1_bit)
# define EXTPOLAR_EXTPOLAR2_FALLING			(EXTPOLAR_EXTPOLAR2_FALLING_value << EXTPOLAR_EXTPOLAR2_bit)
# define EXTPOLAR_EXTPOLAR2_RISING			(EXTPOLAR_EXTPOLAR2_RISING_value << EXTPOLAR_EXTPOLAR2_bit)

/*------------------------------------------------------------------------------
 RSIR - Reset Source Identification Register
------------------------------------------------------------------------------*/
#define RSIR_POR_bit							0
#define RSIR_EXTR_bit						1
#define RSIR_WDTR_bit						2

#define RSIR_POR								(1 << RSIR_POR_bit)
#define RSIR_EXTR								(1 << RSIR_EXTR_bit)
#define RSIR_WDTR								(1 << RSIR_WDTR_bit)

/*------------------------------------------------------------------------------
  AHB priority scheduling
------------------------------------------------------------------------------*/

/*------------------------------------------------------------------------------
 System Control and Status flags register
------------------------------------------------------------------------------*/
# define SCS_GPIO0M_bit 					0
# define SCS_EMC_RESET_bit					1
# define SCS_MCIPWR_bit						3
# define SCS_OSCRANGE_bit 					4
# define SCS_OSCEN_bit 						5
# define SCS_OSCSTAT_bit					6

# define SCS_GPIO0M 							(1 << SCS_GPIO0M_bit)
# define SCS_EMC_RESET						(1 << SCS_EMC_RESET_bit)
# define SCS_MCIPWR							(1 << SCS_MCIPWR_bit)
# define SCS_OSCRANGE 						(1 << SCS_OSCRANGE_bit)
# define SCS_OSCEN 							(1 << SCS_OSCEN_bit)
# define SCS_OSCSTAT 						(1 << SCS_OSCSTAT_bit)

/*------------------------------------------------------------------------------
  IRC Trim register
------------------------------------------------------------------------------*/

/*==============================================================================
 AHB peripherals
==============================================================================*/
/*------------------------------------------------------------------------------
 Ethernet configuration bits
------------------------------------------------------------------------------*/
/* MAC1 bits */
#define MAC_MAC1_RECEIVE_ENABLE_bit 				0
#define MAC_MAC1_PASS_FRAMES_bit 					1
#define MAC_MAC1_RX_FLOW_CONTROL_bit 				2
#define MAC_MAC1_TX_FLOW_CONTROL_bit 				3
#define MAC_MAC1_LOOPBACK_bit 						4
#define MAC_MAC1_TX_RESET_bit 						8
#define MAC_MAC1_TX_MCS_RESET_bit 					9
#define MAC_MAC1_RX_RESET_bit 						10
#define MAC_MAC1_RX_MCS_RESET_bit 					11
#define MAC_MAC1_SIMULATION_RESET_bit 				14
#define MAC_MAC1_SOFT_RESET_bit 						15

#define MAC_MAC1_RECEIVE_ENABLE 						(1 << MAC_MAC1_RECEIVE_ENABLE_bit)
#define MAC_MAC1_PASS_FRAMES							(1 << MAC_MAC1_PASS_FRAMES_bit)
#define MAC_MAC1_RX_FLOW_CONTROL						(1 << MAC_MAC1_RX_FLOW_CONTROL_bit)
#define MAC_MAC1_TX_FLOW_CONTROL	 					(1 << MAC_MAC1_TX_FLOW_CONTROL_bit)
#define MAC_MAC1_LOOPBACK								(1 << MAC_MAC1_LOOPBACK_bit)
#define MAC_MAC1_TX_RESET								(1 << MAC_MAC1_TX_RESET_bit)
#define MAC_MAC1_TX_MCS_RESET							(1 << MAC_MAC1_TX_MCS_RESET_bit)
#define MAC_MAC1_RX_RESET								(1 << MAC_MAC1_RX_RESET_bit)
#define MAC_MAC1_RX_MCS_RESET							(1 << MAC_MAC1_RX_MCS_RESET_bit)
#define MAC_MAC1_SIMULATION_RESET					(1 << MAC_MAC1_SIMULATION_RESET_bit)
#define MAC_MAC1_SOFT_RESET							(1 << MAC_MAC1_SOFT_RESET_bit)

/* MAC2 bits */
#define MAC_MAC2_FULL_DUPLEX_bit 					0
#define MAC_MAC2_FRAME_LENGTH_CHECKING_bit 		1
#define MAC_MAC2_HUGE_FRAME_ENABLE_bit 			2
#define MAC_MAC2_DELAYED_CRC_bit 					3
#define MAC_MAC2_CRC_ENABLE_bit 						4
#define MAC_MAC2_PAD_CRC_ENABLE_bit 				5
#define MAC_MAC2_VLAN_PAD_ENABLE_bit 				6
#define MAC_MAC2_AUTO_DETECT_PAD_ENABLE_bit 		7
#define MAC_MAC2_PURE_PREAMBLE_ENFORCEMENT_bit 	8
#define MAC_MAC2_LONG_PREAMBLE_ENFORCEMENT_bit 	9
#define MAC_MAC2_NO_BACKOFF_bit 						12
#define MAC_MAC2_BACK_PRESSURE_NO_BACKOFF_bit 	13
#define MAC_MAC2_EXCESS_DEFER_bit 					14

#define MAC_MAC2_FULL_DUPLEX							(1 << MAC_MAC2_FULL_DUPLEX_bit)
#define MAC_MAC2_FRAME_LENGTH_CHECKING				(1 << MAC_MAC2_FRAME_LENGTH_CHECKING_bit)
#define MAC_MAC2_HUGE_FRAME_ENABLE					(1 << MAC_MAC2_HUGE_FRAME_ENABLE_bit)
#define MAC_MAC2_DELAYED_CRC							(1 << MAC_MAC2_DELAYED_CRC_bit)
#define MAC_MAC2_CRC_ENABLE							(1 << MAC_MAC2_CRC_ENABLE_bit)
#define MAC_MAC2_PAD_CRC_ENABLE						(1 << MAC_MAC2_PAD_CRC_ENABLE_bit)
#define MAC_MAC2_VLAN_PAD_ENABLE						(1 << MAC_MAC2_VLAN_PAD_ENABLE_bit)
#define MAC_MAC2_AUTO_DETECT_PAD_ENABLE			(1 << MAC_MAC2_AUTO_DETECT_PAD_ENABLE_bit)
#define MAC_MAC2_PURE_PREAMBLE_ENFORCEMENT		(1 << MAC_MAC2_PURE_PREAMBLE_ENFORCEMENT_bit)
#define MAC_MAC2_LONG_PREAMBLE_ENFORCEMENT		(1 << MAC_MAC2_LONG_PREAMBLE_ENFORCEMENT_bit)
#define MAC_MAC2_NO_BACKOFF							(1 << MAC_MAC2_NO_BACKOFF_bit)
#define MAC_MAC2_BACK_PRESSURE_NO_BACKOFF			(1 << MAC_MAC2_BACK_PRESSURE_NO_BACKOFF_bit)
#define MAC_MAC2_EXCESS_DEFER							(1 << MAC_MAC2_EXCESS_DEFER_bit)

/* MAC_COMMAND bits */
#define MAC_COMMAND_RX_ENABLE_bit 					0
#define MAC_COMMAND_TX_ENABLE_bit 					1
#define MAC_COMMAND_REG_RESET_bit 					3
#define MAC_COMMAND_TX_RESET_bit 					4
#define MAC_COMMAND_RX_RESET_bit 					5
#define MAC_COMMAND_PASS_RUNT_FRAME_bit 			6
#define MAC_COMMAND_PASS_RX_FILTER_bit 			7
#define MAC_COMMAND_TX_FLOW_CONTROL_bit 			8
#define MAC_COMMAND_RMII_bit 							9
#define MAC_COMMAND_FULL_DUPLEX_bit 				10

#define MAC_COMMAND_RX_ENABLE							(1 << MAC_COMMAND_RX_ENABLE_bit)
#define MAC_COMMAND_TX_ENABLE							(1 << MAC_COMMAND_TX_ENABLE_bit)
#define MAC_COMMAND_REG_RESET							(1 << MAC_COMMAND_REG_RESET_bit)
#define MAC_COMMAND_TX_RESET							(1 << MAC_COMMAND_TX_RESET_bit)
#define MAC_COMMAND_RX_RESET							(1 << MAC_COMMAND_RX_RESET_bit)
#define MAC_COMMAND_PASS_RUNT_FRAME					(1 << MAC_COMMAND_PASS_RUNT_FRAME_bit)
#define MAC_COMMAND_PASS_RX_FILTER 					(1 << MAC_COMMAND_PASS_RX_FILTER_bit)
#define MAC_COMMAND_TX_FLOW_CONTROL					(1 << MAC_COMMAND_TX_FLOW_CONTROL_bit)
#define MAC_COMMAND_RMII								(1 << MAC_COMMAND_RMII_bit)
#define MAC_COMMAND_FULL_DUPLEX						(1 << MAC_COMMAND_FULL_DUPLEX_bit)

/*------------------------------------------------------------------------------
 IPGR- Non Back-to-Back Inter-Packet Gap Register
 note: the recommended value for bits [6:0] is 0x12 ,
		the recommended value for bits [14:8] is 0xC
------------------------------------------------------------------------------*/
/*
# define MAC_IPGR_PART2_bit0			0
# define MAC_IPGR_PART2_bit1			1
# define MAC_IPGR_PART2_bit2			2
# define MAC_IPGR_PART2_bit3			3
# define MAC_IPGR_PART2_bit4			4
# define MAC_IPGR_PART2_bit5			5
# define MAC_IPGR_PART2_bit6			6

# define MAC_IPGR_PART1_bit8			8
# define MAC_IPGR_PART1_bit9			9
# define MAC_IPGR_PART1_bit10			10
# define MAC_IPGR_PART1_bit11			11
# define MAC_IPGR_PART1_bit12			12
# define MAC_IPGR_PART1_bit13			13
# define MAC_IPGR_PART1_bit14			14
*/
# define MAC_IPGR_PART2 				0x00000012
# define MAC_IPGR_PART1					0x00000C00

/*------------------------------------------------------------------------------
 CLRT- Collision window / Retry register
 note: standard specifies that RETRANSMISSION MAX value [3:0] should be 0xF ,
		the recommended value for COLLISION WINDOW bits [13:8] is 0x37
------------------------------------------------------------------------------*/
/*
# define MAC_CLRT_RETRANSMISSION_MAX_bit0	0
# define MAC_CLRT_RETRANSMISSION_MAX_bit1	1
# define MAC_CLRT_RETRANSMISSION_MAX_bit2	2
# define MAC_CLRT_RETRANSMISSION_MAX_bit3	3

# define MAC_CLRT_COLLISIONl_WINDOW_bit8	8
# define MAC_CLRT_COLLISIONl_WINDOW_bit9	9
# define MAC_CLRT_COLLISIONl_WINDOW_bit10	10
# define MAC_CLRT_COLLISIONl_WINDOW_bit11	11
# define MAC_CLRT_COLLISIONl_WINDOW_bit12	12
# define MAC_CLRT_COLLISIONl_WINDOW_bit13	13
*/

# define MAC_CLRT_RETRANSMISSION_MAX 		0x0000000F
# define MAC_CLRT_COLLISIONl_WINDOW			0x00003700

/*------------------------------------------------------------------------------
 MAXF- Maximum Frame register
 note: bits [15:0] defines a maximum receive frame, the default value is 0x600
------------------------------------------------------------------------------*/
# define MAC_MAXF_MAXIMUM_FRAME_LENGTH		0x00000600

/*------------------------------------------------------------------------------
 MCFG- MII management Configuration register
------------------------------------------------------------------------------*/
# define MAC_MCFG_SCAN_INCREMENT_bit			0
# define MAC_MCFG_SUPPRESS_PREAMBLE_bit		1
# define MAC_MCFG_CLOCK_SELECT_bit0				2
# define MAC_MCFG_CLOCK_SELECT_bit1				3
# define MAC_MCFG_CLOCK_SELECT_bit2				4
# define MAC_MCFG_RESET_MII_MGMT_bit			15

# define MAC_MCFG_SCAN_INCREMENT					(1 << MAC_MCFG_SCAN_INCREMENT_bit)
# define MAC_MCFG_SUPPRESS_PREAMBLE				(1 << MAC_MCFG_SUPPRESS_PREAMBLE_bit)
/* clock divided by 4; 0 0 0 */
# define MAC_MCFG_CLOCK_SELECT_DIV4_value		0x00
/* clock divided by 6; 0 1 0 */
# define MAC_MCFG_CLOCK_SELECT_DIV6_value		0x02
/* clock divided by 8; 0 1 1 */
# define MAC_MCFG_CLOCK_SELECT_DIV8_value		0x03
/* clock divided by 10; 1 0 0 */
# define MAC_MCFG_CLOCK_SELECT_DIV10_value	0x04
/* clock divided by 14; 0 0 0 */
# define MAC_MCFG_CLOCK_SELECT_DIV14_value	0x05
/* clock divided by 20; 1 1 0 */
# define MAC_MCFG_CLOCK_SELECT_DIV20_value	0x06
/* clock divided by 28; 1 1 1 */
# define MAC_MCFG_CLOCK_SELECT_DIV28_value	0x07

# define MAC_MCFG_CLOCK_SELECT_DIV4 		(MAC_MCFG_CLOCK_SELECT_DIV4_value << MAC_MCFG_CLOCK_SELECT_bit0)
# define MAC_MCFG_CLOCK_SELECT_DIV6 		(MAC_MCFG_CLOCK_SELECT_DIV6_value << MAC_MCFG_CLOCK_SELECT_bit0)
# define MAC_MCFG_CLOCK_SELECT_DIV8 		(MAC_MCFG_CLOCK_SELECT_DIV8_value << MAC_MCFG_CLOCK_SELECT_bit0)
# define MAC_MCFG_CLOCK_SELECT_DIV10 		(MAC_MCFG_CLOCK_SELECT_DIV10_value << MAC_MCFG_CLOCK_SELECT_bit0)
# define MAC_MCFG_CLOCK_SELECT_DIV14 		(MAC_MCFG_CLOCK_SELECT_DIV14_value << MAC_MCFG_CLOCK_SELECT_bit0)
# define MAC_MCFG_CLOCK_SELECT_DIV20 		(MAC_MCFG_CLOCK_SELECT_DIV20_value << MAC_MCFG_CLOCK_SELECT_bit0)
# define MAC_MCFG_CLOCK_SELECT_DIV28 		(MAC_MCFG_CLOCK_SELECT_DIV28_value << MAC_MCFG_CLOCK_SELECT_bit0)

# define MAC_MCFG_RESET_MII_MGMT				(1 << MAC_MCFG_RESET_MII_MGMT_bit)

/*------------------------------------------------------------------------------
 MCMD- MII management command register
------------------------------------------------------------------------------*/
# define MAC_MCMD_READ_bit 			0
# define MAC_MCMD_SCAN_bit 			1

# define MAC_MCMD_READ 					(1 << MAC_MCMD_READ_bit) /* single read cycle */
# define MAC_MCMD_SCAN					(1 << MAC_MCMD_SCAN_bit) /* continous read cycles */

/*------------------------------------------------------------------------------
 SUPP- PHY support register
 if SPEED is 0 the speed is 10Mbps, if SPEED is 1; 100 Mbps
------------------------------------------------------------------------------*/
# define MAC_SUPP_SPEED_bit 			8
# define MAC_SUPP_SPEED					(1 << MAC_SUPP_SPEED_bit)

/*------------------------------------------------------------------------------
 MADR- MII management address register
------------------------------------------------------------------------------*/
/*
# define MAC_MADR_REGISTER_ADDRESS_bit0		0
# define MAC_MADR_REGISTER_ADDRESS_bit1		1
# define MAC_MADR_REGISTER_ADDRESS_bit2		2
# define MAC_MADR_REGISTER_ADDRESS_bit3		3
# define MAC_MADR_REGISTER_ADDRESS_bit4		4

# define MAC_MADR_PHY_ADDRESS_bit8			8
# define MAC_MADR_PHY_ADDRESS_bit9			9
# define MAC_MADR_PHY_ADDRESS_bit10			10
# define MAC_MADR_PHY_ADDRESS_bit11			11
# define MAC_MADR_PHY_ADDRESS_bit12			12
*/
/*------------------------------------------------------------------------------
 MWTD- MII management write data register
------------------------------------------------------------------------------*/
/*
# define MAC_MWTD_WRITE_DATA_bit0			0
# define MAC_MWTD_WRITE_DATA_bit1			1
# define MAC_MWTD_WRITE_DATA_bit2			2
# define MAC_MWTD_WRITE_DATA_bit3			3
# define MAC_MWTD_WRITE_DATA_bit4			4
# define MAC_MWTD_WRITE_DATA_bit5			5
# define MAC_MWTD_WRITE_DATA_bit6			6
# define MAC_MWTD_WRITE_DATA_bit7			7
# define MAC_MWTD_WRITE_DATA_bit8			8
# define MAC_MWTD_WRITE_DATA_bit9			9
# define MAC_MWTD_WRITE_DATA_bit10			10
# define MAC_MWTD_WRITE_DATA_bit11			11
# define MAC_MWTD_WRITE_DATA_bit12			12
# define MAC_MWTD_WRITE_DATA_bit13			13
# define MAC_MWTD_WRITE_DATA_bit14			14
# define MAC_MWTD_WRITE_DATA_bit15			15
*/

/*------------------------------------------------------------------------------
 IPGT- Back-To-Back Inter-Packet-Gap Register
------------------------------------------------------------------------------*/
# define MAC_IPGT_HALF_DUPLEX					0x12
# define MAC_IPGT_FULL_DUPLEX					0x15

/*------------------------------------------------------------------------------
 RXFILTERCTRL- Receive Filter Control Register
------------------------------------------------------------------------------*/
# define MAC_RXFILTERCTRL_UCAST_bit			0
# define MAC_RXFILTERCTRL_BCAST_bit			1
# define MAC_RXFILTERCTRL_MCAST_bit			2
# define MAC_RXFILTERCTRL_UCAST_HASH_bit	3
# define MAC_RXFILTERCTRL_MCAST_HASH_bit	4
# define MAC_RXFILTERCTRL_PERFECT_bit		5
# define MAC_RXFILTERCTRL_MAGIC_bit			12
# define MAC_RXFILTERCTRL_RXFILTER_bit		13

# define MAC_RXFILTERCTRL_UCAST				(1 << MAC_RXFILTERCTRL_UCAST_bit)
# define MAC_RXFILTERCTRL_BCAST				(1 << MAC_RXFILTERCTRL_BCAST_bit)
# define MAC_RXFILTERCTRL_MCAST				(1 << MAC_RXFILTERCTRL_MCAST_bit)
# define MAC_RXFILTERCTRL_UCAST_HASH		(1 << MAC_RXFILTERCTRL_UCAST_HASH_bit)
# define MAC_RXFILTERCTRL_MCAST_HASH		(1 << MAC_RXFILTERCTRL_MCAST_HASH_bit)
# define MAC_RXFILTERCTRL_PERFECT			(1 << MAC_RXFILTERCTRL_PERFECT_bit)
# define MAC_RXFILTERCTRL_MAGIC				(1 << MAC_RXFILTERCTRL_MAGIC_bit)
# define MAC_RXFILTERCTRL_RXFILTER			(1 << MAC_RXFILTERCTRL_RXFILTER_bit)

/*------------------------------------------------------------------------------
 INTCLEAR- Interrupt Clear Register
------------------------------------------------------------------------------*/
# define MAC_INTCLEAR_RX_OVERRUN_bit 		0
# define MAC_INTCLEAR_RX_ERR_bit 			1
# define MAC_INTCLEAR_RX_FINISH_bit 		2
# define MAC_INTCLEAR_RX_DONE_bit 			3

# define MAC_INTCLEAR_TX_UNDERRUN_bit 		4
# define MAC_INTCLEAR_TX_ERR_bit 			5
# define MAC_INTCLEAR_TX_FINISH_bit 		6
# define MAC_INTCLEAR_TX_DONE_bit 			7

# define MAC_INTCLEAR_SOFTINT_bit 			12
# define MAC_INTCLEAR_WAKEUPINT_bit 		13


# define MAC_INTCLEAR_RX_OVERRUN				(1 << MAC_INTCLEAR_RX_OVERRUN_bit)
# define MAC_INTCLEAR_RX_ERR					(1 << MAC_INTCLEAR_RX_ERR_bit)
# define MAC_INTCLEAR_RX_FINISH				(1 << MAC_INTCLEAR_RX_FINISH_bit)
# define MAC_INTCLEAR_RX_DONE					(1 << MAC_INTCLEAR_RX_DONE_bit)

# define MAC_INTCLEAR_TX_UNDERRUN			(1 << MAC_INTCLEAR_TX_UNDERRUN_bit)
# define MAC_INTCLEAR_TX_ERR					(1 << MAC_INTCLEAR_TX_ERR_bit)
# define MAC_INTCLEAR_TX_FINISH				(1 << MAC_INTCLEAR_TX_FINISH_bit)
# define MAC_INTCLEAR_TX_DONE					(1 << MAC_INTCLEAR_TX_DONE_bit)

# define MAC_INTCLEAR_SOFTINT					(1 << MAC_INTCLEAR_SOFTINT_bit)
# define MAC_INTCLEAR_WAKEUPINT				(1 << MAC_INTCLEAR_WAKEUPINT_bit)

/*------------------------------------------------------------------------------
 GPDMA- General Purpose Direct Memory Access registers
------------------------------------------------------------------------------*/
# define GPDMA_INT_STAT_INT_STATUS0_bit			0
# define GPDMA_INT_STAT_INT_STATUS1_bit			1
# define GPDMA_INT_STAT_INT_STATUS0					(1 << GPDMA_INT_STAT_INT_STATUS0_bit)
# define GPDMA_INT_STAT_INT_STATUS1					(1 << GPDMA_INT_STAT_INT_STATUS1_bit)

# define GPDMA_INT_TCSTAT_INT_TCSTATUS0_bit		0
# define GPDMA_INT_TCSTAT_INT_TCSTATUS1_bit		1
# define GPDMA_INT_TCSTAT_INT_TCSTATUS0			(1 << GPDMA_INT_TCSTAT_INT_TCSTATUS0_bit)
# define GPDMA_INT_TCSTAT_INT_TCSTATUS1			(1 << GPDMA_INT_TCSTAT_INT_TCSTATUS1_bit)

# define GPDMA_INT_TCCLR_INT_TCCLR0_bit			0
# define GPDMA_INT_TCCLR_INT_TCCLR1_bit			1
# define GPDMA_INT_TCCLR_INT_TCCLR0					(1 << GPDMA_INT_TCCLR_INT_TCCLR0_bit)
# define GPDMA_INT_TCCLR_INT_TCCLR1					(1 << GPDMA_INT_TCCLR_INT_TCCLR1_bit)

# define GPDMA_INT_ERR_STAT_INT_ERR0_bit			0
# define GPDMA_INT_ERR_STAT_INT_ERR1_bit			1
# define GPDMA_INT_ERR_STAT_INT_ERR0				(1 << GPDMA_INT_ERR_STAT_INT_ERR0_bit)
# define GPDMA_INT_ERR_STAT_INT_ERR1				(1 << GPDMA_INT_ERR_STAT_INT_ERR1_bit)

# define GPDMA_INT_ERR_CLR_INT_ERR0_bit			0
# define GPDMA_INT_ERR_CLR_INT_ERR1_bit			1
# define GPDMA_INT_ERR_CLR_INT_ERR0					(1 << GPDMA_INT_ERR_CLR_INT_ERR0_bit)
# define GPDMA_INT_ERR_CLR_INT_ERR1					(1 <<  GPDMA_INT_ERR_CLR_INT_ERR1_bit)

# define GPDMA_RAW_INT_TCSTAT_RAW_INT_TC0_bit	0
# define GPDMA_RAW_INT_TCSTAT_RAW_INT_TC1_bit	1
# define GPDMA_RAW_INT_TCSTAT_RAW_INT_TC0			(1 << GPDMA_RAW_INT_TCSTAT_RAW_INT_TC0_bit)
# define GPDMA_RAW_INT_TCSTAT_RAW_INT_TC1			(1 << GPDMA_RAW_INT_TCSTAT_RAW_INT_TC1_bit)

# define GPDMA_RAW_INT_ERR_STAT_ERR0_bit			0
# define GPDMA_RAW_INT_ERR_STAT_ERR1_bit			1
# define GPDMA_RAW_INT_ERR_STAT_ERR0				(1 << GPDMA_RAW_INT_ERR_STAT_ERR0_bit)
# define GPDMA_RAW_INT_ERR_STAT_ERR1				(1 << GPDMA_RAW_INT_ERR_STAT_ERR1_bit)

# define GPDMA_ENABLED_CHNS_ENABLED_CH0_bit		0
# define GPDMA_ENABLED_CHNS_ENABLED_CH1_bit		1
# define GPDMA_ENABLED_CHNS_ENABLED_CH0			(1 << GPDMA_ENABLED_CHNS_ENABLED_CH0_bit)
# define GPDMA_ENABLED_CHNS_ENABLED_CH1			(1 << GPDMA_ENABLED_CHNS_ENABLED_CH1_bit)

# define GPDMA_SOFT_BREQ_SSP0_TX_bit				0
# define GPDMA_SOFT_BREQ_SSP0_RX_bit				1
# define GPDMA_SOFT_BREQ_SSP1_TX_bit				2
# define GPDMA_SOFT_BREQ_SSP1_RX_bit				3
# define GPDMA_SOFT_BREQ_SD_MMC_bit					4
# define GPDMA_SOFT_BREQ_I2S0_bit					5
# define GPDMA_SOFT_BREQ_I2S1_bit					6
# define GPDMA_SOFT_BREQ_SSP0_TX						(1 << GPDMA_SOFT_BREQ_SSP0_TX_bit)
# define GPDMA_SOFT_BREQ_SSP0_RX						(1 << GPDMA_SOFT_BREQ_SSP0_RX_bit)
# define GPDMA_SOFT_BREQ_SSP1_TX						(1 << GPDMA_SOFT_BREQ_SSP1_TX_bit)
# define GPDMA_SOFT_BREQ_SSP1_RX						(1 << GPDMA_SOFT_BREQ_SSP1_RX_bit)
# define GPDMA_SOFT_BREQ_SD_MMC						(1 << GPDMA_SOFT_BREQ_SD_MMC_bit)
# define GPDMA_SOFT_BREQ_I2S0							(1 << GPDMA_SOFT_BREQ_I2S0_bit)
# define GPDMA_SOFT_BREQ_I2S1							(1 << GPDMA_SOFT_BREQ_I2S1_bit)

# define GPDMA_SOFT_SREQ_SSP0_TX_bit			0
# define GPDMA_SOFT_SREQ_SSP0_RX_bit			1
# define GPDMA_SOFT_SREQ_SSP1_TX_bit			2
# define GPDMA_SOFT_SREQ_SSP1_RX_bit			3
# define GPDMA_SOFT_SREQ_SD_MMC_bit				4
# define GPDMA_SOFT_SREQ_SSP0_TX					(1 << GPDMA_SOFT_SREQ_SSP0_TX_bit)
# define GPDMA_SOFT_SREQ_SSP0_RX					(1 << GPDMA_SOFT_SREQ_SSP0_RX_bit)
# define GPDMA_SOFT_SREQ_SSP1_TX					(1 << GPDMA_SOFT_SREQ_SSP1_TX_bit)
# define GPDMA_SOFT_SREQ_SSP1_RX					(1 << GPDMA_SOFT_SREQ_SSP1_RX_bit)
# define GPDMA_SOFT_SREQ_SD_MMC					(1 << GPDMA_SOFT_SREQ_SD_MMC_bit)

# define GPDMA_SOFT_LBREQ_SD_MMC_bit			4
# define GPDMA_SOFT_LBREQ_SD_MMC					(1 << GPDMA_SOFT_LBREQ_SD_MMC_bit)

# define GPDMA_SOFT_LSREQ_SD_MMC_bit			4
# define GPDMA_SOFT_LSREQ_SD_MMC					(1 << GPDMA_SOFT_LSREQ_SD_MMC_bit)

# define GPDMA_CONFIG_ENABLE_bit					0
# define GPDMA_CONFIG_BIG_ENDIAN_bit			1
# define GPDMA_CONFIG_ENABLE						(1 << GPDMA_CONFIG_ENABLE_bit)
# define GPDMA_CONFIG_BIG_ENDIAN					(1 << GPDMA_CONFIG_BIG_ENDIAN_bit) /* Big endian */

/* channel bits */
# define GPDMA_CH_CTRL_TRANSFER_SIZE_bit		0
# define GPDMA_CH_CTRL_SB_SIZE_bit				12						/* source burst size */
# define GPDMA_CH_CTRL_DB_SIZE_bit				15						/* destination burst size */
# define GPDMA_CH_CTRL_SWIDTH_bit				18						/* source transfer width */
# define GPDMA_CH_CTRL_DWIDTH_bit				21						/* destination transfer width */
# define GPDMA_CH_CTRL_SI_bit						26						/* source increment */
# define GPDMA_CH_CTRL_DI_bit						27						/* destination increment */
# define GPDMA_CH_CTRL_PROT_bit					28						/* protection */
# define GPDMA_CH_CTRL_I_bit						31						/* terminal count interrupt enable bit */
# define GPDMA_CH_CTRL_TRANSFER_SIZE_mask		0x0FFF					/* 11:0 bit */

# define GPDMA_CH_CTRL_SB_SIZE_1_value			0x00
# define GPDMA_CH_CTRL_SB_SIZE_4_value			0x01
# define GPDMA_CH_CTRL_SB_SIZE_8_value			0x02
# define GPDMA_CH_CTRL_SB_SIZE_16_value		0x03
# define GPDMA_CH_CTRL_SB_SIZE_32_value		0x04
# define GPDMA_CH_CTRL_SB_SIZE_64_value		0x05
# define GPDMA_CH_CTRL_SB_SIZE_128_value		0x06
# define GPDMA_CH_CTRL_SB_SIZE_256_value		0x07

# define GPDMA_CH_CTRL_DB_SIZE_1_value			0x00
# define GPDMA_CH_CTRL_DB_SIZE_4_value			0x01
# define GPDMA_CH_CTRL_DB_SIZE_8_value			0x02
# define GPDMA_CH_CTRL_DB_SIZE_16_value		0x03
# define GPDMA_CH_CTRL_DB_SIZE_32_value		0x04
# define GPDMA_CH_CTRL_DB_SIZE_64_value		0x05
# define GPDMA_CH_CTRL_DB_SIZE_128_value		0x06
# define GPDMA_CH_CTRL_DB_SIZE_256_value		0x07

# define GPDMA_CH_CTRL_SWIDTH_8_value			0x00
# define GPDMA_CH_CTRL_SWIDTH_16_value			0x01
# define GPDMA_CH_CTRL_SWIDTH_32_value			0x02

# define GPDMA_CH_CTRL_DWIDTH_8_value			0x00
# define GPDMA_CH_CTRL_DWIDTH_16_value			0x01
# define GPDMA_CH_CTRL_DWIDTH_32_value			0x02

# define GPDMA_CH_CTRL_SB_SIZE_1					(GPDMA_CH_CTRL_SB_SIZE_1_value << GPDMA_CH_CTRL_SB_SIZE_bit)
# define GPDMA_CH_CTRL_SB_SIZE_4					(GPDMA_CH_CTRL_SB_SIZE_4_value << GPDMA_CH_CTRL_SB_SIZE_bit)
# define GPDMA_CH_CTRL_SB_SIZE_8					(GPDMA_CH_CTRL_SB_SIZE_8_value << GPDMA_CH_CTRL_SB_SIZE_bit)
# define GPDMA_CH_CTRL_SB_SIZE_16				(GPDMA_CH_CTRL_SB_SIZE_16_value << GPDMA_CH_CTRL_SB_SIZE_bit)
# define GPDMA_CH_CTRL_SB_SIZE_32				(GPDMA_CH_CTRL_SB_SIZE_32_value << GPDMA_CH_CTRL_SB_SIZE_bit)
# define GPDMA_CH_CTRL_SB_SIZE_64				(GPDMA_CH_CTRL_SB_SIZE_64_value << GPDMA_CH_CTRL_SB_SIZE_bit)
# define GPDMA_CH_CTRL_SB_SIZE_128				(GPDMA_CH_CTRL_SB_SIZE_128_value << GPDMA_CH_CTRL_SB_SIZE_bit)
# define GPDMA_CH_CTRL_SB_SIZE_256				(GPDMA_CH_CTRL_SB_SIZE_256_value << GPDMA_CH_CTRL_SB_SIZE_bit)

# define GPDMA_CH_CTRL_DB_SIZE_1					(GPDMA_CH_CTRL_DB_SIZE_1_value << GPDMA_CH_CTRL_DB_SIZE_bit)
# define GPDMA_CH_CTRL_DB_SIZE_4					(GPDMA_CH_CTRL_DB_SIZE_4_value << GPDMA_CH_CTRL_DB_SIZE_bit)
# define GPDMA_CH_CTRL_DB_SIZE_8					(GPDMA_CH_CTRL_DB_SIZE_8_value << GPDMA_CH_CTRL_DB_SIZE_bit)
# define GPDMA_CH_CTRL_DB_SIZE_16				(GPDMA_CH_CTRL_DB_SIZE_16_value << GPDMA_CH_CTRL_DB_SIZE_bit)
# define GPDMA_CH_CTRL_DB_SIZE_32				(GPDMA_CH_CTRL_DB_SIZE_32_value << GPDMA_CH_CTRL_DB_SIZE_bit)
# define GPDMA_CH_CTRL_DB_SIZE_64				(GPDMA_CH_CTRL_DB_SIZE_64_value << GPDMA_CH_CTRL_DB_SIZE_bit)
# define GPDMA_CH_CTRL_DB_SIZE_128				(GPDMA_CH_CTRL_DB_SIZE_128_value << GPDMA_CH_CTRL_DB_SIZE_bit)
# define GPDMA_CH_CTRL_DB_SIZE_256				(GPDMA_CH_CTRL_DB_SIZE_256_value << GPDMA_CH_CTRL_DB_SIZE_bit)

# define GPDMA_CH_CTRL_SWIDTH_8					(GPDMA_CH_CTRL_SWIDTH_8_value << GPDMA_CH_CTRL_SWIDTH_bit)
# define GPDMA_CH_CTRL_SWIDTH_16					(GPDMA_CH_CTRL_SWIDTH_16_value << GPDMA_CH_CTRL_SWIDTH_bit)
# define GPDMA_CH_CTRL_SWIDTH_32					(GPDMA_CH_CTRL_SWIDTH_32_value << GPDMA_CH_CTRL_SWIDTH_bit)

# define GPDMA_CH_CTRL_DWIDTH_8					(GPDMA_CH_CTRL_DWIDTH_8_value << GPDMA_CH_CTRL_DWIDTH_bit)
# define GPDMA_CH_CTRL_DWIDTH_16					(GPDMA_CH_CTRL_DWIDTH_16_value << GPDMA_CH_CTRL_DWIDTH_bit)
# define GPDMA_CH_CTRL_DWIDTH_32					(GPDMA_CH_CTRL_DWIDTH_32_value << GPDMA_CH_CTRL_DWIDTH_bit)

# define GPDMA_CH_CTRL_SI							(1 << GPDMA_CH_CTRL_SI_bit)
# define GPDMA_CH_CTRL_DI							(1 << GPDMA_CH_CTRL_DI_bit)
//# define GPDMA_CH_CTRL_PROT
# define GPDMA_CH_CTRL_I							(1 << GPDMA_CH_CTRL_I_bit)

# define GPDMA_CH_CFG_CHANNEL_EN_bit				0
# define GPDMA_CH_CFG_SRC_PERIPH_bit				1
# define GPDMA_CH_CFG_SRC_PERIPH_SSP0TX_value	0
# define GPDMA_CH_CFG_SRC_PERIPH_SSP0RX_value	1
# define GPDMA_CH_CFG_SRC_PERIPH_SSP1TX_value	2
# define GPDMA_CH_CFG_SRC_PERIPH_SSP1RX_value	3
# define GPDMA_CH_CFG_SRC_PERIPH_SD_value			4
# define GPDMA_CH_CFG_SRC_PERIPH_I2S0_value		5
# define GPDMA_CH_CFG_SRC_PERIPH_I2S1_value		6
# define GPDMA_CH_CFG_DST_PERIPH_bit				6
# define GPDMA_CH_CFG_DST_PERIPH_SSP0TX_value	0
# define GPDMA_CH_CFG_DST_PERIPH_SSP0RX_value	1
# define GPDMA_CH_CFG_DST_PERIPH_SSP1TX_value	2
# define GPDMA_CH_CFG_DST_PERIPH_SSP1RX_value	3
# define GPDMA_CH_CFG_DST_PERIPH_SD_value			4
# define GPDMA_CH_CFG_DST_PERIPH_I2S0_value		5
# define GPDMA_CH_CFG_DST_PERIPH_I2S1_value		6
# define GPDMA_CH_CFG_FLOW_CTRL_bit					11
# define GPDMA_CH_CFG_FLOW_CTRL_M2M_DMA_value	0
# define GPDMA_CH_CFG_FLOW_CTRL_M2P_DMA_value	1
# define GPDMA_CH_CFG_FLOW_CTRL_P2M_DMA_value	2
# define GPDMA_CH_CFG_FLOW_CTRL_SP2DP_DMA_value	3		/* Src peripheral 2 dest peripheral */
# define GPDMA_CH_CFG_FLOW_CTRL_SP2DP_DP_value	4
# define GPDMA_CH_CFG_FLOW_CTRL_M2P_P_value		5
# define GPDMA_CH_CFG_FLOW_CTRL_P2M_P_value		6
# define GPDMA_CH_CFG_FLOW_CTRL_SP2DP_SP_value	7
# define GPDMA_CH_CFG_IE_bit							14
# define GPDMA_CH_CFG_ITC_bit							15
# define GPDMA_CH_CFG_LOCK_bit						16
# define GPDMA_CH_CFG_ACTIVE_bit						17
# define GPDMA_CH_CFG_HALT_bit						18
# define GPDMA_CH_CFG_CHANNEL_EN						(1 << GPDMA_CH_CFG_CHANNEL_EN_bit)
# define GPDMA_CH_CFG_SRC_PERIPH_SSP0TX			(GPDMA_CH_CFG_SRC_PERIPH_SSP0TX_value << GPDMA_CH_CFG_SRC_PERIPH_bit)
# define GPDMA_CH_CFG_SRC_PERIPH_SSP0RX			(GPDMA_CH_CFG_SRC_PERIPH_SSP0RX_value << GPDMA_CH_CFG_SRC_PERIPH_bit)
# define GPDMA_CH_CFG_SRC_PERIPH_SSP1TX			(GPDMA_CH_CFG_SRC_PERIPH_SSP1TX_value << GPDMA_CH_CFG_SRC_PERIPH_bit)
# define GPDMA_CH_CFG_SRC_PERIPH_SSP1RX			(GPDMA_CH_CFG_SRC_PERIPH_SSP1RX_value << GPDMA_CH_CFG_SRC_PERIPH_bit)
# define GPDMA_CH_CFG_SRC_PERIPH_SD					(GPDMA_CH_CFG_SRC_PERIPH_SD_value << GPDMA_CH_CFG_SRC_PERIPH_bit)
# define GPDMA_CH_CFG_SRC_PERIPH_I2S0				(GPDMA_CH_CFG_SRC_PERIPH_I2S0_value << GPDMA_CH_CFG_SRC_PERIPH_bit)
# define GPDMA_CH_CFG_SRC_PERIPH_I2S1				(GPDMA_CH_CFG_SRC_PERIPH_I2S1_value << GPDMA_CH_CFG_SRC_PERIPH_bit)
# define GPDMA_CH_CFG_DST_PERIPH_SSP0TX			(GPDMA_CH_CFG_DST_PERIPH_SSP0TX_value << GPDMA_CH_CFG_DST_PERIPH_bit)
# define GPDMA_CH_CFG_DST_PERIPH_SSP0RX			(GPDMA_CH_CFG_DST_PERIPH_SSP0RX_value << GPDMA_CH_CFG_DST_PERIPH_bit)
# define GPDMA_CH_CFG_DST_PERIPH_SSP1TX			(GPDMA_CH_CFG_DST_PERIPH_SSP1TX_value << GPDMA_CH_CFG_DST_PERIPH_bit)
# define GPDMA_CH_CFG_DST_PERIPH_SSP1RX			(GPDMA_CH_CFG_DST_PERIPH_SSP1RX_value << GPDMA_CH_CFG_DST_PERIPH_bit)
# define GPDMA_CH_CFG_DST_PERIPH_SD					(GPDMA_CH_CFG_DST_PERIPH_SD_value << GPDMA_CH_CFG_DST_PERIPH_bit)
# define GPDMA_CH_CFG_DST_PERIPH_I2S0				(GPDMA_CH_CFG_DST_PERIPH_I2S0_value << GPDMA_CH_CFG_DST_PERIPH_bit)
# define GPDMA_CH_CFG_DST_PERIPH_I2S1				(GPDMA_CH_CFG_DST_PERIPH_I2S1_value << GPDMA_CH_CFG_DST_PERIPH_bit)
# define GPDMA_CH_CFG_FLOW_CTRL_M2M_DMA			(GPDMA_CH_CFG_FLOW_CTRL_M2M_DMA_value << GPDMA_CH_CFG_FLOW_CTRL_bit)
# define GPDMA_CH_CFG_FLOW_CTRL_M2P_DMA			(GPDMA_CH_CFG_FLOW_CTRL_M2P_DMA_value << GPDMA_CH_CFG_FLOW_CTRL_bit)
# define GPDMA_CH_CFG_FLOW_CTRL_P2M_DMA			(GPDMA_CH_CFG_FLOW_CTRL_P2M_DMA_value << GPDMA_CH_CFG_FLOW_CTRL_bit)
# define GPDMA_CH_CFG_FLOW_CTRL_SP2DP_DMA			(GPDMA_CH_CFG_FLOW_CTRL_SP2DP_DMA_value << GPDMA_CH_CFG_FLOW_CTRL_bit)
# define GPDMA_CH_CFG_FLOW_CTRL_SP2DP_DP			(GPDMA_CH_CFG_FLOW_CTRL_SP2DP_DP_value << GPDMA_CH_CFG_FLOW_CTRL_bit)
# define GPDMA_CH_CFG_FLOW_CTRL_M2P_P				(GPDMA_CH_CFG_FLOW_CTRL_M2P_P_value << GPDMA_CH_CFG_FLOW_CTRL_bit)
# define GPDMA_CH_CFG_FLOW_CTRL_P2M_P				(GPDMA_CH_CFG_FLOW_CTRL_P2M_P_value << GPDMA_CH_CFG_FLOW_CTRL_bit)
# define GPDMA_CH_CFG_FLOW_CTRL_SP2DP_SP			(GPDMA_CH_CFG_FLOW_CTRL_SP2DP_SP_value << GPDMA_CH_CFG_FLOW_CTRL_bit)
# define GPDMA_CH_CFG_IE								(1 << GPDMA_CH_CFG_IE_bit)
# define GPDMA_CH_CFG_ITC								(1 << GPDMA_CH_CFG_ITC_bit)
# define GPDMA_CH_CFG_LOCK								(1 << GPDMA_CH_CFG_LOCK_bit)
# define GPDMA_CH_CFG_ACTIVE							(1 << GPDMA_CH_CFG_ACTIVE_bit)
# define GPDMA_CH_CFG_HALT								(1 << GPDMA_CH_CFG_HALT_bit)

/*------------------------------------------------------------------------------
 External Memory Controller (EMC Control)
------------------------------------------------------------------------------*/
# define EMC_CTRL_EMC_ENABLE_bit			0
# define EMC_CTRL_ADDRESS_MIRROR_bit	1
# define EMC_CTRL_LOW_POWER_MODE_bit	2
# define EMC_CTRL_EMC_ENABLE				(1 << EMC_CTRL_EMC_ENABLE_bit)
# define EMC_CTRL_ADDRESS_MIRROR			(1 << EMC_CTRL_ADDRESS_MIRROR_bit)
# define EMC_CTRL_LOW_POWER_MODE			(1 << EMC_CTRL_LOW_POWER_MODE_bit)

/* Static Memory Configuration registers (EMCStaticConfig0-3) */
# define EMC_STA_CFG0_MEMORY_WIDTH_bit			0
# define EMC_STA_CFG0_MEMORY_WIDTH8_value		0
# define EMC_STA_CFG0_MEMORY_WIDTH16_value	1
# define EMC_STA_CFG0_MEMORY_WIDTH32_value	2
# define EMC_STA_CFG0_PAGE_MODE_bit				3
# define EMC_STA_CFG0_SELECT_POLARITY_bit		6
# define EMC_STA_CFG0_BYTE_LANE_STATE_bit		7
# define EMC_STA_CFG0_EXTENDED_WAIT_bit		8
# define EMC_STA_CFG0_BUFFER_ENABLE_bit		19
# define EMC_STA_CFG0_WRITE_PROTECT_bit		20
# define EMC_STA_CFG0_MEMORY_WIDTH8				(EMC_STA_CFG0_MEMORY_WIDTH8_value << EMC_STA_CFG0_MEMORY_WIDTH_bit)
# define EMC_STA_CFG0_MEMORY_WIDTH16			(EMC_STA_CFG0_MEMORY_WIDTH16_value << EMC_STA_CFG0_MEMORY_WIDTH_bit)
# define EMC_STA_CFG0_MEMORY_WIDTH32			(EMC_STA_CFG0_MEMORY_WIDTH32_value << EMC_STA_CFG0_MEMORY_WIDTH_bit)
# define EMC_STA_CFG0_PAGE_MODE					(1 << EMC_STA_CFG0_PAGE_MODE_bit)
# define EMC_STA_CFG0_SELECT_POLARITY			(1 << EMC_STA_CFG0_SELECT_POLARITY_bit)
# define EMC_STA_CFG0_BYTE_LANE_STATE			(1 << EMC_STA_CFG0_BYTE_LANE_STATE_bit)
# define EMC_STA_CFG0_EXTENDED_WAIT				(1 << EMC_STA_CFG0_EXTENDED_WAIT_bit)
# define EMC_STA_CFG0_BUFFER_ENABLE				(1 << EMC_STA_CFG0_BUFFER_ENABLE_bit)
# define EMC_STA_CFG0_WRITE_PROTECT				(1 << EMC_STA_CFG0_WRITE_PROTECT_bit)

/*------------------------------------------------------------------------------
 PCLKSEL0
------------------------------------------------------------------------------*/
# define PCLKSEL0_WTD_bit                 0
# define PCLKSEL0_TIMER0_bit              2
# define PCLKSEL0_TIMER1_bit              4
# define PCLKSEL0_UART0_bit               6
# define PCLKSEL0_UART1_bit               8
# define PCLKSEL0_PWM0_bit                10
# define PCLKSEL0_PWM1_bit                12
# define PCLKSEL0_I2C0_bit                14
# define PCLKSEL0_SPI_bit                 16
# define PCLKSEL0_RTC_bit                 18
# define PCLKSEL0_SSP1_bit                20
# define PCLKSEL0_DAC_bit                 22
# define PCLKSEL0_ADC_bit                 24
# define PCLKSEL0_CAN1_bit                26
# define PCLKSEL0_CAN2_bit                28
# define PCLKSEL0_ACF_bit                 30
/******************************************************************************
* END OF FILE
******************************************************************************/
#endif /* HDR_SCB_H_ */
